Ignoring Diagnostic Test Failures

You can ignore diagnostic test failures on the line module or SRP. This enables you to categorize diagnostic failures and determine the impact on functional behavior.

To ignore diagnostic test failure on the line module or SRP:

  1. Select the slot number of the slot that you want to ignore diagnostic test failure. This information is stored on the SRP and is independent of the hardware in the slot. You can reload a particular slot to boot the module to the operational image.
    host1#slot ignore-diagnostic-failure 0
  2. Issue the show environment command to check which line modules are configured to ignore diagnostics test failure.
    host1#show environment
    chassis: 14 slot (id 0x5, rev. 0x1)
        fabric: 40 Gbps (rev. 0)
        fans: fanSubsystemOk
        nvs: ok (488MB flash disk, 43% full), matches running config
        power: A ok, B not present
        srp redundancy: mode is high-availability, state initializing
            auto-sync enabled, switch-on-error enabled
            sync in progress
        slots: ok
            online: 0 6 12
            standby: 7
            empty: 1 2 3 4 5 8 9 10 11 13
            diagnostic failure is ignored on slot: 0 
        line redundancy: none
        temperature: ok
        timing: primary
            primary: internal SC oscillator (ok)
            secondary: internal SC oscillator (ok)
            tertiary: internal SC oscillator (ok)
            auto-upgrade enabled
        system operational: yes
  3. Issue the no version of the command to return to the default setting for the slot:
    host1(config)# no slot ignore-diagnostic-failure 12
  4. Issue the show environment command to check that the slot no longer ignores diagnostic test failures :
    host1#show environment    chassis: 14 slot (id 0x5, rev. 0x1)
        fabric: 40 Gbps (rev. 0)
        fans: fanSubsystemOk
        nvs: ok (488MB flash disk, 43% full), matches running config
        power: A ok, B not present
        srp redundancy: mode is high-availability, state initializing
            auto-sync enabled, switch-on-error enabled
            sync in progress
        slots: ok
            online: 0 6 12
            standby: 7
            empty: 1 2 3 4 5 8 9 10 11 13
            diagnostic failure is ignored on slot: 0,6,7 
        line redundancy: none
        temperature: ok
        timing: primary
            primary: internal SC oscillator (ok)
            secondary: internal SC oscillator (ok)
            tertiary: internal SC oscillator (ok)
            auto-upgrade enabled
        system operational: yes

If an SRP failure occurs when the router boots from the factory defaults or when your configuration is lost, you can ignore test failures from the boot menu:

  1. From the boot prompt, issue the option ignore-srp-diagnostic-results command.
    :boot##option ignore-srp-diagnostic-results
  2. Verify that the setting is correct:
    :boot##show options
        no option auto-boot-disable
           option countdown
        no option debug-startup
        no option halt-on-failure
        no option bypass-diagnostics
        no option stay-in-diagnostics
           option ignore-srp-diagnostic-results
        no option instruction-cache-disable
        no option watchdog-disable
        no option redirect-serial
        no option diagnostics-burn-in
        no option start-wdb
        no option start-standby-wdb
        no option assertions-in
        no option memory-debug
        no option disable-backpress
        no option stl-debug
    

Note: In the burn-in mode, the done bit of the configuration (CFG) register is used to detect the blank PROM. When the FPGA for SFM module is being loaded, the system examines whether the done bit is set for blank PROMs. In the burn-in mode, if the done bit is not set, the testing utility halts and the FPGA is not programmed. At this point, the system displays a message stating that the done bit is not set for the blank PROM. If the done bit has been previously set for blank PROMs, the test that is performed successfully completes and the programming of the FPGA continues.

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