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show chassis fabric topology

Syntax

show chassis fabric topology<lcc number | scc> <sib-slot>

Syntax (TX Matrix Router)

show chassis fabric topology<lcc number | scc> <sib-slot>

Syntax (TX Matrix Plus Router)

show chassis fabric topology<lcc number | sfc number> <sib-slot>

Syntax (T4000 Core Router)

show chassis fabric topology<sib-slot>

Syntax (PTX Series Packet Transport Switches)

show chassis fabric topology

Release Information

Command introduced before Junos OS Release 7.4.

sfc option introduced for the TX Matrix Plus router in Junos OS Release 9.6.

Command introduced in Junos OS Release 12.1 for PTX Series Packet Transport Switches.

Description

(TX Matrix routers only) Display the state of the switching fabric topology for the Switch Interface Board (SIB) connection between the TX Matrix router and the T640 routers.

(TX Matrix Plus routers only) Display the state of the switching fabric topology for the SIB connection between the TX Matrix Plus router and the T1600 routers.

(T320, T640, T1600, and T4000 routers only) Display the state of the switching fabric topology for the connection between the Switch Interface Board (SIB) and the FPCs.

(PTX Series Packet Transport Switches only) Display the input-output link topology.

Options

none

—

(TX Matrix routers only) Display the state of the switching fabric topology for the Switch Interface Board (SIB) connection between the TX Matrix router and the T640 routers.

(TX Matrix Plus routers only) Display the state of the switching fabric topology for the SIB connection between the TX Matrix Plus router and the T1600 routers.

(T320, T640, T1600, and T4000 routers only) Display the state of the switching fabric topology for the connection between the Switch Interface Board (SIB) and the FPCs.

lcc number

—

(TX Matrix and TX Matrix Plus routers only) (Optional) On a TX Matrix router, display the fabric topology state for a specified T640 router (or line-card chassis) that is connected to a TX Matrix router. On a TX Matrix Plus router, display the fabric topology state for a specified T1600 router (or line-card chassis) that is connected to the TX Matrix Plus router. Replace number with a value from 0 through 3.

scc

—

(TX Matrix routers only) (Optional) Display the fabric topology state for the TX Matrix router (or switch-card chassis).

sfc number

—

(TX Matrix Plus routers only) (Optional) Display the fabric topology for the TX Matrix Plus router (or switch-fabric chassis). Replace number with 0.

sib-slot

—

(Optional) Display the fabric topology state for a specified SIB slot. Replace sib-slot with a value from 0 through 4. On a TX Matrix Plus router, replace sib-slot with a value from 0 through 15.

Required Privilege Level

view

Related Documentation

Layer 2 Wholesale Network Topology Overview

List of Sample Output

show chassis fabric topology scc (TX Matrix Router)
show chassis fabric topology lcc
show chassis fabric topology (TX Matrix Plus Router)
show chassis fabric topology sfc (TX Matrix Plus Router)
show chassis fabric topology lcc (TX Matrix Plus Router)
show chassis fabric topology (T4000 Core Router)
show chassis fabric topology (PTX Series Packet Transport Switches)

Output Fields

Table 1 lists the output fields for the show chassis fabric topology command. Output fields are listed in the approximate order in which they appear.

Table 1: show chassis fabric topology Output Fields

Field Name	Field Description
in-links	Fabric topology for receive side links.
out-links	Fabric topology for transmit side links.
state	State of the fabric link: RESET—Link between the SIB and the FPC/DPC is powered down on purpose. This is done in all non-dual Packet Forwarding Engine–based boards. UP—Link between the SIB and the FPC/DCP is up and running. DOWN—Link between the SIB and the FPC/DCP is powered down. FAULT—The SIB is in the alarmed state, in which the SIB’s plane is not operational for one or more of the following reasons: On-board F-chip is not operational. Fiber-optic connector faults. FPC connector faults. SIB midplane connector faults. Note: The following state descriptions are applicable only to PTX Series Packet Transport Switches. OK—The link between the SIB and the FPC is operational. Down—The link between the SIB and the FPC is powered down. Error—The CCL link between the SIB and FPC is not operational for one or more of the following reasons: FPC midplane connector failure. SIB midplane connector failure. CCL link CRC error.

Out-Links: and In-Links (TX Matrix Plus router only)	State of the links from the F13 SIB to the LCC or vice-versa. Out-Links indicate Tx links. In-Links indicate an Rx link. The following additional fields are displayed for each SIB:
	VCSEL Status—Optical (VCSEL channel) link status for the corresponding electrical (HSL2) link. The states include: OK—Optical signal power is good. Error—Internal error. LOS—Loss of Signal detected. High Cur—The Tx Bias-current is higher than threshold on this channel. This is applicable only to Tx Channels. Low Cur —The Tx Bias-current is lower than threshold on this channel. This is applicable only to Tx Channels. HSL2 Channel—HSL2 is the electrical link used to connect ASICs to the in-link and out-link. The channel number corresponds to the link and varies based on the ASIC or configuration.
	HSL2 Status —The status of the HSL2 Channel. Includes the following states: Up—Channel is up. Down—Channel is down. Reset—Channel has been reset. Fault—Channel has faults. The following is a sample output with description of the fields displayed in the output for Out-Links: Out-Links: ========= SF_30_13_FB_A(21,09) -> FPC7_B_SG(3,3,6)_FB_A(18,09) OK 203 Up
	SF_30_13—Name of the ASIC, with Fabric F1 or F3 mode. In this case, 3 is the F3 direction and is used in the Tx path and 0 identifies the serial link on the SF chip (in this case, link goes to sf-3 chip number 0). You can also have F1 mode and Rx path instead. FB_A (21, 09)—Fiber bundle A, with VCSEL unit number 21 within the SIB, and channel number 9 within the unit number. FPC7_B_SG(3,3,6—FPC 7.with bottom Packet Forwarding Engine (T for top PFE and B for bottom PFE), SG ASIC, with number 3 and port number 3, with HSL2 link number with the SIB as 6. FB_A(18, 09)—Fiber Bundle, with VCSEL unit number 18 within the SIB, and VCSEL channel number 9 within the unit number. The following is a sample output with description of the fields displayed in the output for In-Links: In-Links: ========= FPC0_T_SG(0,0,0)_FB_D(04,11) -> SF_10_00_FB_D(01,11) OK 0 Up FPC0—FPC 0. T—Top Packet Forwarding Engine. SG (0, 0, 0)—SG ASIC with port number 0 and link 0. FB_D (04,11)—Fiber Bundle D with VCSEL 4, channel 11. SF_10—Indicates F1 mode chip number 0 and Rx path. SF_10_00_FB_D(01,11) —Indicates F1 mode chip number 0 and Rx path with port 0, fiber bundle D, with VCSEL 1, channel 11.

Sample Output

show chassis fabric topology scc (TX Matrix Router)

user@host> show chassis fabric topology scc

scc-re1:
--------------------------------------------------------------------------------
fchip (mode)
in-links								state 		out-links 								state
-------------------------------------------------------------------------------- 
Sib #0 :
---------
SIB0_F0 (F2 ):
LCC0_SIB-L0_F0,03->SIB-S0_F0,00	 UP 								SIB-S0_F0,00->LCC0_SIB-L0_F1,00  UP
LCC1_SIB-L0_F0,03->SIB-S0_F0,01	 UP 								SIB-S0_F0,01->LCC1_SIB-L0_F1,08  UP
LCC2_SIB-L0_F0,03->SIB-S0_F0,02	 RESET							SIB-S0_F0,02->LCC2_SIB-L0_F1,08  UP
LCC3_SIB-L0_F0,03->SIB-S0_F0,03	 RESET							SIB-S0_F0,03->LCC3_SIB-L0_F1,00  UP
LCC0_SIB-L0_F0,02->SIB-S0_F0,04  UP 								SIB-S0_F0,04->LCC0_SIB-L0_F1,01  UP
LCC1_SIB-L0_F0,02->SIB-S0_F0,05  UP 								SIB-S0_F0,05->LCC1_SIB-L0_F1,09  UP
LCC2_SIB-L0_F0,02->SIB-S0_F0,06  RESET							SIB-S0_F0,06->LCC2_SIB-L0_F1,09  UP
LCC3_SIB-L0_F0,02->SIB-S0_F0,07  RESET							SIB-S0_F0,07->LCC3_SIB-L0_F1,01  UP
LCC0_SIB-L0_F0,07->SIB-S0_F0,08  UP 								SIB-S0_F0,08->LCC0_SIB-L0_F1,04  UP
LCC1_SIB-L0_F0,07->SIB-S0_F0,09  UP 								SIB-S0_F0,09->LCC1_SIB-L0_F1,12  UP
LCC2_SIB-L0_F0,07->SIB-S0_F0,10  RESET							SIB-S0_F0,10->LCC2_SIB-L0_F1,12  UP
LCC3_SIB-L0_F0,07->SIB-S0_F0,11  RESET							SIB-S0_F0,11->LCC3_SIB-L0_F1,04  UP
LCC0_SIB-L0_F0,06->SIB-S0_F0,12  UP 								SIB-S0_F0,12->LCC0_SIB-L0_F1,05  UP
LCC1_SIB-L0_F0,06->SIB-S0_F0,13  UP 								SIB-S0_F0,13->LCC1_SIB-L0_F1,13  UP
LCC2_SIB-L0_F0,06->SIB-S0_F0,14  RESET							SIB-S0_F0,14->LCC2_SIB-L0_F1,13  UP
LCC3_SIB-L0_F0,06->SIB-S0_F0,15  RESET							SIB-S0_F0,15->LCC3_SIB-L0_F1,05  UP
SIB0_F1 (F2 ):
LCC0_SIB-L0_F0,11->SIB-S0_F1,00  UP 								SIB-S0_F1,00->LCC0_SIB-L0_F1,08  UP
LCC1_SIB-L0_F0,11->SIB-S0_F1,01  UP 								SIB-S0_F1,01->LCC1_SIB-L0_F1,00  UP
LCC2_SIB-L0_F0,11->SIB-S0_F1,02  RESET							SIB-S0_F1,02->LCC2_SIB-L0_F1,00  UP
LCC3_SIB-L0_F0,11->SIB-S0_F1,03  RESET							SIB-S0_F1,03->LCC3_SIB-L0_F1,08  UP
LCC0_SIB-L0_F0,10->SIB-S0_F1,04  UP 								SIB-S0_F1,04->LCC0_SIB-L0_F1,09  UP
LCC1_SIB-L0_F0,10->SIB-S0_F1,05  UP 								SIB-S0_F1,05->LCC1_SIB-L0_F1,01  UP
LCC2_SIB-L0_F0,10->SIB-S0_F1,06  RESET							SIB-S0_F1,06->LCC2_SIB-L0_F1,01  UP
LCC3_SIB-L0_F0,10->SIB-S0_F1,07  RESET							SIB-S0_F1,07->LCC3_SIB-L0_F1,09  UP
LCC0_SIB-L0_F0,15->SIB-S0_F1,08  UP 								SIB-S0_F1,08->LCC0_SIB-L0_F1,12  UP
LCC1_SIB-L0_F0,15->SIB-S0_F1,09  UP 								SIB-S0_F1,09->LCC1_SIB-L0_F1,04  UP
LCC2_SIB-L0_F0,15->SIB-S0_F1,10  RESET							SIB-S0_F1,10->LCC2_SIB-L0_F1,04  UP
LCC3_SIB-L0_F0,15->SIB-S0_F1,11  RESET							SIB-S0_F1,11->LCC3_SIB-L0_F1,12  UP
LCC0_SIB-L0_F0,14->SIB-S0_F1,12  UP 								SIB-S0_F1,12->LCC0_SIB-L0_F1,13  UP
LCC1_SIB-L0_F0,14->SIB-S0_F1,13  UP 								SIB-S0_F1,13->LCC1_SIB-L0_F1,05  UP
LCC2_SIB-L0_F0,14->SIB-S0_F1,14  RESET 							SIB-S0_F1,14->LCC2_SIB-L0_F1,05  UP
LCC3_SIB-L0_F0,14->SIB-S0_F1,15  RESET 							SIB-S0_F1,15->LCC3_SIB-L0_F1,13  UP
SIB0_F2 (F2 ):
LCC3_SIB-L0_F0,13->SIB-S0_F2,00 		RESET 					SIB-S0_F2,00->LCC3_SIB-L0_F1,14  UP
LCC2_SIB-L0_F0,13->SIB-S0_F2,01  RESET 							SIB-S0_F2,01->LCC2_SIB-L0_F1,06  UP
LCC1_SIB-L0_F0,13->SIB-S0_F2,02  UP 								SIB-S0_F2,02->LCC1_SIB-L0_F1,06  UP
LCC0_SIB-L0_F0,13->SIB-S0_F2,03  UP 								SIB-S0_F2,03->LCC0_SIB-L0_F1,14  UP
LCC3_SIB-L0_F0,12->SIB-S0_F2,04  RESET 							SIB-S0_F2,04->LCC3_SIB-L0_F1,15  UP
LCC2_SIB-L0_F0,12->SIB-S0_F2,05  RESET							SIB-S0_F2,05->LCC2_SIB-L0_F1,07  UP
LCC1_SIB-L0_F0,12->SIB-S0_F2,06  UP 								SIB-S0_F2,06->LCC1_SIB-L0_F1,07  UP
LCC0_SIB-L0_F0,12->SIB-S0_F2,07  UP 								SIB-S0_F2,07->LCC0_SIB-L0_F1,15  UP
LCC3_SIB-L0_F0,09->SIB-S0_F2,08  RESET 							SIB-S0_F2,08->LCC3_SIB-L0_F1,10  UP
LCC2_SIB-L0_F0,09->SIB-S0_F2,09  RESET 							SIB-S0_F2,09->LCC2_SIB-L0_F1,02  UP
LCC1_SIB-L0_F0,09->SIB-S0_F2,10  UP 								SIB-S0_F2,10->LCC1_SIB-L0_F1,02  UP
LCC0_SIB-L0_F0,09->SIB-S0_F2,11  UP 								SIB-S0_F2,11->LCC0_SIB-L0_F1,10  UP
LCC3_SIB-L0_F0,08->SIB-S0_F2,12  RESET 							SIB-S0_F2,12->LCC3_SIB-L0_F1,11  UP
LCC2_SIB-L0_F0,08->SIB-S0_F2,13  RESET 							SIB-S0_F2,13->LCC2_SIB-L0_F1,03  UP
LCC1_SIB-L0_F0,08->SIB-S0_F2,14	 UP 								SIB-S0_F2,14->LCC1_SIB-L0_F1,03  UP
LCC0_SIB-L0_F0,08->SIB-S0_F2,15  UP 								SIB-S0_F2,15->LCC0_SIB-L0_F1,11  UP
SIB0_F3 (F2 ):
LCC3_SIB-L0_F0,05->SIB-S0_F3,00  RESET 							SIB-S0_F3,00->LCC3_SIB-L0_F1,06  UP
LCC2_SIB-L0_F0,05->SIB-S0_F3,01  RESET 							SIB-S0_F3,01->LCC2_SIB-L0_F1,14  UP
LCC1_SIB-L0_F0,05->SIB-S0_F3,02  UP 								SIB-S0_F3,02->LCC1_SIB-L0_F1,14  UP
LCC0_SIB-L0_F0,05->SIB-S0_F3,03  UP 								SIB-S0_F3,03->LCC0_SIB-L0_F1,06  UP
LCC3_SIB-L0_F0,04->SIB-S0_F3,04  RESET 							SIB-S0_F3,04->LCC3_SIB-L0_F1,07  UP
LCC2_SIB-L0_F0,04->SIB-S0_F3,05  RESET 							SIB-S0_F3,05->LCC2_SIB-L0_F1,15  UP
LCC1_SIB-L0_F0,04->SIB-S0_F3,06  UP 								SIB-S0_F3,06->LCC1_SIB-L0_F1,15  UP
LCC0_SIB-L0_F0,04->SIB-S0_F3,07  UP 								SIB-S0_F3,07->LCC0_SIB-L0_F1,07  UP
LCC3_SIB-L0_F0,01->SIB-S0_F3,08  RESET 							SIB-S0_F3,08->LCC3_SIB-L0_F1,02  UP
LCC2_SIB-L0_F0,01->SIB-S0_F3,09  RESET 							SIB-S0_F3,09->LCC2_SIB-L0_F1,10  UP
LCC1_SIB-L0_F0,01->SIB-S0_F3,10  UP 								SIB-S0_F3,10->LCC1_SIB-L0_F1,10  UP
LCC0_SIB-L0_F0,01->SIB-S0_F3,11  UP 								SIB-S0_F3,11->LCC0_SIB-L0_F1,02  UP
LCC3_SIB-L0_F0,00->SIB-S0_F3,12  RESET 							SIB-S0_F3,12->LCC3_SIB-L0_F1,03  UP
LCC2_SIB-L0_F0,00->SIB-S0_F3,13  RESET 							SIB-S0_F3,13->LCC2_SIB-L0_F1,11  UP
LCC1_SIB-L0_F0,00->SIB-S0_F3,14  UP 								SIB-S0_F3,14->LCC1_SIB-L0_F1,11  UP
LCC0_SIB-L0_F0,00->SIB-S0_F3,15  UP 								SIB-S0_F3,15->LCC0_SIB-L0_F1,03  UP
Sib #1 :
---------
SIB1_F0 (F2 ):
LCC0_SIB-L1_F0,03->SIB-S1_F0,00 RESET 							SIB-S1_F0,00->LCC0_SIB-L1_F1,00  UP
LCC1_SIB-L1_F0,03->SIB-S1_F0,01 RESET 							SIB-S1_F0,01->LCC1_SIB-L1_F1,08  UP
LCC2_SIB-L1_F0,03->SIB-S1_F0,02 RESET 							SIB-S1_F0,02->LCC2_SIB-L1_F1,08  UP
LCC3_SIB-L1_F0,03->SIB-S1_F0,03 RESET 							SIB-S1_F0,03->LCC3_SIB-L1_F1,00  UP
LCC0_SIB-L1_F0,02->SIB-S1_F0,04 RESET 							SIB-S1_F0,04->LCC0_SIB-L1_F1,01  UP
LCC1_SIB-L1_F0,02->SIB-S1_F0,05 RESET 							SIB-S1_F0,05->LCC1_SIB-L1_F1,09  UP
LCC2_SIB-L1_F0,02->SIB-S1_F0,06 RESET 							SIB-S1_F0,06->LCC2_SIB-L1_F1,09  UP
LCC3_SIB-L1_F0,02->SIB-S1_F0,07 RESET 							SIB-S1_F0,07->LCC3_SIB-L1_F1,01  UP
LCC0_SIB-L1_F0,07->SIB-S1_F0,08 RESET 							SIB-S1_F0,08->LCC0_SIB-L1_F1,04  UP
LCC1_SIB-L1_F0,07->SIB-S1_F0,09 RESET 							SIB-S1_F0,09->LCC1_SIB-L1_F1,12  UP
LCC2_SIB-L1_F0,07->SIB-S1_F0,10 RESET 							SIB-S1_F0,10->LCC2_SIB-L1_F1,12	 UP
LCC3_SIB-L1_F0,07->SIB-S1_F0,11 RESET 							SIB-S1_F0,11->LCC3_SIB-L1_F1,04	 UP
LCC0_SIB-L1_F0,06->SIB-S1_F0,12 RESET 							SIB-S1_F0,12->LCC0_SIB-L1_F1,05  UP
LCC1_SIB-L1_F0,06->SIB-S1_F0,13 RESET 							SIB-S1_F0,13->LCC1_SIB-L1_F1,13  UP
LCC2_SIB-L1_F0,06->SIB-S1_F0,14 RESET 							SIB-S1_F0,14->LCC2_SIB-L1_F1,13  UP
LCC3_SIB-L1_F0,06->SIB-S1_F0,15 RESET 							SIB-S1_F0,15->LCC3_SIB-L1_F1,05  UP
SIB1_F1 (F2 ):
LCC0_SIB-L1_F0,11->SIB-S1_F1,00 RESET 							SIB-S1_F1,00->LCC0_SIB-L1_F1,08  UP
LCC1_SIB-L1_F0,11->SIB-S1_F1,01 RESET 							SIB-S1_F1,01->LCC1_SIB-L1_F1,00  UP
LCC2_SIB-L1_F0,11->SIB-S1_F1,02 RESET 							SIB-S1_F1,02->LCC2_SIB-L1_F1,00  UP
LCC3_SIB-L1_F0,11->SIB-S1_F1,03 RESET 							SIB-S1_F1,03->LCC3_SIB-L1_F1,08  UP
LCC0_SIB-L1_F0,10->SIB-S1_F1,04 RESET 							SIB-S1_F1,04->LCC0_SIB-L1_F1,09	 UP
LCC1_SIB-L1_F0,10->SIB-S1_F1,05 RESET								SIB-S1_F1,05->LCC1_SIB-L1_F1,01  UP
LCC2_SIB-L1_F0,10->SIB-S1_F1,06 RESET 							SIB-S1_F1,06->LCC2_SIB-L1_F1,01  UP
LCC3_SIB-L1_F0,10->SIB-S1_F1,07 RESET 							SIB-S1_F1,07->LCC3_SIB-L1_F1,09  UP
LCC0_SIB-L1_F0,15->SIB-S1_F1,08 RESET 							SIB-S1_F1,08->LCC0_SIB-L1_F1,12  UP
LCC1_SIB-L1_F0,15->SIB-S1_F1,09 RESET 							SIB-S1_F1,09->LCC1_SIB-L1_F1,04  UP
LCC2_SIB-L1_F0,15->SIB-S1_F1,10 RESET 							SIB-S1_F1,10->LCC2_SIB-L1_F1,04  UP
LCC3_SIB-L1_F0,15->SIB-S1_F1,11 RESET 							-S1_F1,11->LCC3_SIB-L1_F1,12,05  UP
LCC0_SIB-L1_F0,14->SIB-S1_F1,12 RESET 							SIB-S1_F1,12->LCC0_SIB-L1_F1,13  UP
LCC1_SIB-L1_F0,14->SIB-S1_F1,13 RESET 							SIB-S1_F1,13->LCC1_SIB-L1_F1,05  UP
LCC2_SIB-L1_F0,14->SIB-S1_F1,14 RESET 							SIB-S1_F1,14->LCC2_SIB-L1_F1,05  UP

show chassis fabric topology lcc

user@host> show chassis fabric topology lcc
0

lcc0-re0:
--------------------------------------------------------------------------
   fchip (mode)
in-links                state         out-links               state
-------------------------------------------------------------------
Sib #2 :
---------
SIB2_F0  (F1 ):
FPC0_T->SIB-L2_F0,00    DOWN       SIB-L2_F0,00->SIB-S2_F3,15 DOWN
FPC0_B->SIB-L2_F0,01    UP         SIB-L2_F0,01->SIB-S2_F3,11 DOWN
FPC1_T->SIB-L2_F0,02    DOWN       SIB-L2_F0,02->SIB-S2_F0,04 DOWN
FPC1_B->SIB-L2_F0,03    DOWN       SIB-L2_F0,03->SIB-S2_F0,00 DOWN
FPC2_T->SIB-L2_F0,04    DOWN       SIB-L2_F0,04->SIB-S2_F3,07 DOWN
FPC2_B->SIB-L2_F0,05    DOWN       SIB-L2_F0,05->SIB-S2_F3,03 DOWN
FPC3_T->SIB-L2_F0,06    DOWN       SIB-L2_F0,06->SIB-S2_F0,12 DOWN
FPC3_B->SIB-L2_F0,07    DOWN       SIB-L2_F0,07->SIB-S2_F0,08 DOWN
FPC4_T->SIB-L2_F0,08    DOWN       SIB-L2_F0,08->SIB-S2_F2,15 DOWN
FPC4_B->SIB-L2_F0,09    DOWN       SIB-L2_F0,09->SIB-S2_F2,11 DOWN
FPC5_T->SIB-L2_F0,10    DOWN       SIB-L2_F0,10->SIB-S2_F1,04 DOWN
FPC5_B->SIB-L2_F0,11    DOWN       SIB-L2_F0,11->SIB-S2_F1,00 DOWN
FPC6_T->SIB-L2_F0,12    DOWN       SIB-L2_F0,12->SIB-S2_F2,07 DOWN
FPC6_B->SIB-L2_F0,13    UP         SIB-L2_F0,13->SIB-S2_F2,03 DOWN
FPC7_T->SIB-L2_F0,14    DOWN       SIB-L2_F0,14->SIB-S2_F1,12 DOWN
FPC7_B->SIB-L2_F0,15    DOWN       SIB-L2_F0,15->SIB-S2_F1,08 DOWN
SIB2_F1  (F3 ):
SIB-S2_F0,00->SIB-L2_F1,00 UP      SIB-L2_F1,00->FPC7_B    DOWN
SIB-S2_F0,04->SIB-L2_F1,01 UP      SIB-L2_F1,01->FPC7_T    DOWN
SIB-S2_F3,11->SIB-L2_F1,02 UP      SIB-L2_F1,02->FPC6_B    DOWN
SIB-S2_F3,15->SIB-L2_F1,03 UP      SIB-L2_F1,03->FPC6_T    DOWN
SIB-S2_F0,08->SIB-L2_F1,04 UP      SIB-L2_F1,04->FPC5_B    DOWN
SIB-S2_F0,12->SIB-L2_F1,05 UP      SIB-L2_F1,05->FPC5_T    DOWN
SIB-S2_F3,03->SIB-L2_F1,06 UP      SIB-L2_F1,06->FPC4_B    DOWN
SIB-S2_F3,07->SIB-L2_F1,07 UP      SIB-L2_F1,07->FPC4_T    DOWN
SIB-S2_F1,00->SIB-L2_F1,08 UP      SIB-L2_F1,08->FPC3_B    DOWN
SIB-S2_F1,04->SIB-L2_F1,09 UP      SIB-L2_F1,09->FPC3_T    DOWN
SIB-S2_F2,11->SIB-L2_F1,10 UP      SIB-L2_F1,10->FPC2_B    DOWN
SIB-S2_F2,15->SIB-L2_F1,11 UP      SIB-L2_F1,11->FPC2_T    DOWN
SIB-S2_F1,08->SIB-L2_F1,12 UP      SIB-L2_F1,12->FPC1_B    DOWN
SIB-S2_F1,12->SIB-L2_F1,13 UP      SIB-L2_F1,13->FPC1_T    DOWN
SIB-S2_F2,03->SIB-L2_F1,14 UP      SIB-L2_F1,14->FPC0_B    DOWN
SIB-S2_F2,07->SIB-L2_F1,15 UP      SIB-L2_F1,15->FPC0_T    DOWN
Sib #4 :
---------
SIB4_F0  (F1 ):
FPC0_T->SIB-L4_F0,00    RESET      SIB-L4_F0,00->SIB-S4_F3,15 UP
FPC0_B->SIB-L4_F0,01    UP         SIB-L4_F0,01->SIB-S4_F3,11 UP
FPC1_T->SIB-L4_F0,02    RESET      SIB-L4_F0,02->SIB-S4_F0,04 UP
FPC1_B->SIB-L4_F0,03    RESET      SIB-L4_F0,03->SIB-S4_F0,00 UP
FPC2_T->SIB-L4_F0,04    RESET      SIB-L4_F0,04->SIB-S4_F3,07 UP
FPC2_B->SIB-L4_F0,05    RESET      SIB-L4_F0,05->SIB-S4_F3,03 UP
FPC3_T->SIB-L4_F0,06    RESET      SIB-L4_F0,06->SIB-S4_F0,12 UP
FPC3_B->SIB-L4_F0,07    RESET      SIB-L4_F0,07->SIB-S4_F0,08 UP
FPC4_T->SIB-L4_F0,08    RESET      SIB-L4_F0,08->SIB-S4_F2,15 UP
FPC4_B->SIB-L4_F0,09    RESET      SIB-L4_F0,09->SIB-S4_F2,11 UP
FPC5_T->SIB-L4_F0,10    RESET      SIB-L4_F0,10->SIB-S4_F1,04 UP
FPC5_B->SIB-L4_F0,11    RESET      SIB-L4_F0,11->SIB-S4_F1,00 UP
FPC6_T->SIB-L4_F0,12    RESET      SIB-L4_F0,12->SIB-S4_F2,07 UP
FPC6_B->SIB-L4_F0,13    UP         SIB-L4_F0,13->SIB-S4_F2,03 UP
FPC7_T->SIB-L4_F0,14    RESET      SIB-L4_F0,14->SIB-S4_F1,12 UP
FPC7_B->SIB-L4_F0,15    RESET      SIB-L4_F0,15->SIB-S4_F1,08 UP
SIB4_F1  (F3 ):
SIB-S4_F0,00->SIB-L4_F1,00 UP      SIB-L4_F1,00->FPC7_B    UP
SIB-S4_F0,04->SIB-L4_F1,01 UP      SIB-L4_F1,01->FPC7_T    UP
SIB-S4_F3,11->SIB-L4_F1,02 UP      SIB-L4_F1,02->FPC6_B    UP
SIB-S4_F3,15->SIB-L4_F1,03 UP      SIB-L4_F1,03->FPC6_T    UP
SIB-S4_F0,08->SIB-L4_F1,04 UP      SIB-L4_F1,04->FPC5_B    UP
SIB-S4_F0,12->SIB-L4_F1,05 UP      SIB-L4_F1,05->FPC5_T    UP
SIB-S4_F3,03->SIB-L4_F1,06 UP      SIB-L4_F1,06->FPC4_B    UP
SIB-S4_F3,07->SIB-L4_F1,07 UP      SIB-L4_F1,07->FPC4_T    UP
SIB-S4_F1,00->SIB-L4_F1,08 UP      SIB-L4_F1,08->FPC3_B    UP
SIB-S4_F1,04->SIB-L4_F1,09 UP      SIB-L4_F1,09->FPC3_T    UP
SIB-S4_F2,11->SIB-L4_F1,10 UP      SIB-L4_F1,10->FPC2_B    UP
SIB-S4_F2,15->SIB-L4_F1,11 UP      SIB-L4_F1,11->FPC2_T    UP
SIB-S4_F1,08->SIB-L4_F1,12 UP      SIB-L4_F1,12->FPC1_B    UP
SIB-S4_F1,12->SIB-L4_F1,13 UP      SIB-L4_F1,13->FPC1_T    UP
SIB-S4_F2,03->SIB-L4_F1,14 UP      SIB-L4_F1,14->FPC0_B    UP
SIB-S4_F2,07->SIB-L4_F1,15 UP      SIB-L4_F1,15->FPC0_T    UP

show chassis fabric topology (TX Matrix Plus Router)

user@host> show chassis fabric topology

sfc0-re0:
--------------------------------------------------------------------------

F13_SIB0 
=========

Out-Links:
=========
SFC0_F13_SIB_00      -> LCC00_ST_SIB_L00                 VCSEL    HSL2    HSL2
                                                         Status   Channel Status
================================================================================
SF_30_00_FB_D(04,11) -> FPC0_T_SG(0,0,0)_FB_D(01,11)     OK       112     Up   
SF_30_00_FB_D(04,10) -> FPC0_T_SG(0,0,1)_FB_D(01,10)     OK       112     Up   
SF_30_00_FB_D(04,09) -> FPC0_T_SG(0,0,2)_FB_D(01,09)     OK       112     Up   
SF_30_00_FB_D(04,08) -> FPC0_T_SG(0,0,3)_FB_D(01,08)     OK       112     Up   
SF_30_00_FB_D(04,07) -> FPC0_T_SG(0,0,4)_FB_D(01,07)     OK       112     Up   
SF_30_00_FB_D(04,06) -> FPC0_T_SG(0,0,5)_FB_D(01,06)     OK       112     Up   
SF_30_00_FB_D(04,05) -> FPC0_T_SG(0,0,6)_FB_D(01,05)     OK       112     Up   
SF_30_00_FB_D(04,04) -> FPC0_T_SG(0,0,7)_FB_D(01,04)     OK       112     Up   
SF_30_01_FB_B(16,11) -> FPC4_T_SG(2,0,0)_FB_B(13,11)     OK       119     Up   
SF_30_01_FB_B(16,10) -> FPC4_T_SG(2,0,1)_FB_B(13,10)     OK       119     Up   
SF_30_01_FB_B(16,09) -> FPC4_T_SG(2,0,2)_FB_B(13,09)     OK       119     Up   
SF_30_01_FB_B(16,08) -> FPC4_T_SG(2,0,3)_FB_B(13,08)     OK       119     Up   
SF_30_01_FB_B(16,07) -> FPC4_T_SG(2,0,4)_FB_B(13,07)     OK       119     Up   
SF_30_01_FB_B(16,06) -> FPC4_T_SG(2,0,5)_FB_B(13,06)     OK       119     Up   
SF_30_01_FB_B(16,05) -> FPC4_T_SG(2,0,6)_FB_B(13,05)     OK       119     Up   
SF_30_01_FB_B(16,04) -> FPC4_T_SG(2,0,7)_FB_B(13,04)     OK       119     Up   
SF_30_02_FB_D(05,08) -> FPC1_T_SG(0,2,0)_FB_D(02,08)     OK       126     Up   
SF_30_02_FB_D(05,07) -> FPC1_T_SG(0,2,1)_FB_D(02,07)     OK       126     Up   
SF_30_02_FB_D(05,06) -> FPC1_T_SG(0,2,2)_FB_D(02,06)     OK       126     Up   
SF_30_02_FB_D(05,05) -> FPC1_T_SG(0,2,3)_FB_D(02,05)     OK       126     Up   
SF_30_02_FB_D(05,03) -> FPC1_T_SG(0,2,4)_FB_D(02,03)     OK       126     Up   
SF_30_02_FB_D(05,02) -> FPC1_T_SG(0,2,5)_FB_D(02,02)     OK       126     Up   
SF_30_02_FB_D(05,01) -> FPC1_T_SG(0,2,6)_FB_D(02,01)     OK       126     Up   
SF_30_02_FB_D(05,00) -> FPC1_T_SG(0,2,7)_FB_D(02,00)     OK       126     Up   
SF_30_03_FB_B(17,08) -> FPC5_T_SG(2,2,0)_FB_B(14,08)     OK       133     Up   
SF_30_03_FB_B(17,07) -> FPC5_T_SG(2,2,1)_FB_B(14,07)     OK       133     Up   
SF_30_03_FB_B(17,06) -> FPC5_T_SG(2,2,2)_FB_B(14,06)     OK       133     Up   
SF_30_03_FB_B(17,05) -> FPC5_T_SG(2,2,3)_FB_B(14,05)     OK       133     Up   
SF_30_03_FB_B(17,03) -> FPC5_T_SG(2,2,4)_FB_B(14,03)     OK       133     Up   
SF_30_03_FB_B(17,02) -> FPC5_T_SG(2,2,5)_FB_B(14,02)     OK       133     Up   
SF_30_03_FB_B(17,01) -> FPC5_T_SG(2,2,6)_FB_B(14,01)     OK       133     Up   
SF_30_03_FB_B(17,00) -> FPC5_T_SG(2,2,7)_FB_B(14,00)     OK       133     Up   
SF_30_04_FB_C(10,11) -> FPC2_T_SG(1,0,0)_FB_C(07,11)     OK       140     Up   
SF_30_04_FB_C(10,10) -> FPC2_T_SG(1,0,1)_FB_C(07,10)     OK       140     Up   
SF_30_04_FB_C(10,09) -> FPC2_T_SG(1,0,2)_FB_C(07,09)     OK       140     Up   
SF_30_04_FB_C(10,08) -> FPC2_T_SG(1,0,3)_FB_C(07,08)     OK       140     Up   
SF_30_04_FB_C(10,07) -> FPC2_T_SG(1,0,4)_FB_C(07,07)     OK       140     Up   
SF_30_04_FB_C(10,06) -> FPC2_T_SG(1,0,5)_FB_C(07,06)     OK       140     Up   
SF_30_04_FB_C(10,05) -> FPC2_T_SG(1,0,6)_FB_C(07,05)     OK       140     Up   
SF_30_04_FB_C(10,04) -> FPC2_T_SG(1,0,7)_FB_C(07,04)     OK       140     Up   
SF_30_05_FB_A(22,11) -> FPC6_T_SG(3,0,0)_FB_A(19,11)     OK       147     Up   
SF_30_05_FB_A(22,10) -> FPC6_T_SG(3,0,1)_FB_A(19,10)     OK       147     Up   
SF_30_05_FB_A(22,09) -> FPC6_T_SG(3,0,2)_FB_A(19,09)     OK       147     Up   
SF_30_05_FB_A(22,08) -> FPC6_T_SG(3,0,3)_FB_A(19,08)     OK       147     Up   
SF_30_05_FB_A(22,07) -> FPC6_T_SG(3,0,4)_FB_A(19,07)     OK       147     Up   
SF_30_05_FB_A(22,06) -> FPC6_T_SG(3,0,5)_FB_A(19,06)     OK       147     Up   
SF_30_05_FB_A(22,05) -> FPC6_T_SG(3,0,6)_FB_A(19,05)     OK       147     Up   
SF_30_05_FB_A(22,04) -> FPC6_T_SG(3,0,7)_FB_A(19,04)     OK       147     Up   
SF_30_06_FB_C(11,08) -> FPC3_T_SG(1,2,0)_FB_C(08,08)     OK       154     Up   
SF_30_06_FB_C(11,07) -> FPC3_T_SG(1,2,1)_FB_C(08,07)     OK       154     Up   
SF_30_06_FB_C(11,06) -> FPC3_T_SG(1,2,2)_FB_C(08,06)     OK       154     Up   
SF_30_06_FB_C(11,05) -> FPC3_T_SG(1,2,3)_FB_C(08,05)     OK       154     Up   
SF_30_06_FB_C(11,03) -> FPC3_T_SG(1,2,4)_FB_C(08,03)     OK       154     Up   
SF_30_06_FB_C(11,02) -> FPC3_T_SG(1,2,5)_FB_C(08,02)     OK       154     Up   
SF_30_06_FB_C(11,01) -> FPC3_T_SG(1,2,6)_FB_C(08,01)     OK       154     Up   
SF_30_06_FB_C(11,00) -> FPC3_T_SG(1,2,7)_FB_C(08,00)     OK       154     Up 
…

show chassis fabric topology sfc (TX Matrix Plus Router)

user@host> show chassis fabric topology sfc 0

sfc0-re0:
--------------------------------------------------------------------------

F13_SIB0 
=========

Out-Links:
=========
SFC0_F13_SIB_00      -> LCC00_ST_SIB_L00                 VCSEL    HSL2    HSL2
                                                         Status   Channel Status
================================================================================
SF_30_00_FB_D(04,11) -> FPC0_T_SG(0,0,0)_FB_D(01,11)     OK       112     Up   
SF_30_00_FB_D(04,10) -> FPC0_T_SG(0,0,1)_FB_D(01,10)     OK       112     Up   
SF_30_00_FB_D(04,09) -> FPC0_T_SG(0,0,2)_FB_D(01,09)     OK       112     Up   
SF_30_00_FB_D(04,08) -> FPC0_T_SG(0,0,3)_FB_D(01,08)     OK       112     Up   
SF_30_00_FB_D(04,07) -> FPC0_T_SG(0,0,4)_FB_D(01,07)     OK       112     Up   
SF_30_00_FB_D(04,06) -> FPC0_T_SG(0,0,5)_FB_D(01,06)     OK       112     Up   
SF_30_00_FB_D(04,05) -> FPC0_T_SG(0,0,6)_FB_D(01,05)     OK       112     Up   
SF_30_00_FB_D(04,04) -> FPC0_T_SG(0,0,7)_FB_D(01,04)     OK       112     Up   
SF_30_01_FB_B(16,11) -> FPC4_T_SG(2,0,0)_FB_B(13,11)     OK       119     Up   
SF_30_01_FB_B(16,10) -> FPC4_T_SG(2,0,1)_FB_B(13,10)     OK       119     Up   
SF_30_01_FB_B(16,09) -> FPC4_T_SG(2,0,2)_FB_B(13,09)     OK       119     Up   
SF_30_01_FB_B(16,08) -> FPC4_T_SG(2,0,3)_FB_B(13,08)     OK       119     Up   
SF_30_01_FB_B(16,07) -> FPC4_T_SG(2,0,4)_FB_B(13,07)     OK       119     Up   
SF_30_01_FB_B(16,06) -> FPC4_T_SG(2,0,5)_FB_B(13,06)     OK       119     Up   
SF_30_01_FB_B(16,05) -> FPC4_T_SG(2,0,6)_FB_B(13,05)     OK       119     Up   
SF_30_01_FB_B(16,04) -> FPC4_T_SG(2,0,7)_FB_B(13,04)     OK       119     Up   
SF_30_02_FB_D(05,08) -> FPC1_T_SG(0,2,0)_FB_D(02,08)     OK       126     Up   
SF_30_02_FB_D(05,07) -> FPC1_T_SG(0,2,1)_FB_D(02,07)     OK       126     Up   
SF_30_02_FB_D(05,06) -> FPC1_T_SG(0,2,2)_FB_D(02,06)     OK       126     Up   
SF_30_02_FB_D(05,05) -> FPC1_T_SG(0,2,3)_FB_D(02,05)     OK       126     Up   
SF_30_02_FB_D(05,03) -> FPC1_T_SG(0,2,4)_FB_D(02,03)     OK       126     Up   
SF_30_02_FB_D(05,02) -> FPC1_T_SG(0,2,5)_FB_D(02,02)     OK       126     Up   
SF_30_02_FB_D(05,01) -> FPC1_T_SG(0,2,6)_FB_D(02,01)     OK       126     Up   
SF_30_02_FB_D(05,00) -> FPC1_T_SG(0,2,7)_FB_D(02,00)     OK       126     Up   
SF_30_03_FB_B(17,08) -> FPC5_T_SG(2,2,0)_FB_B(14,08)     OK       133     Up   
SF_30_03_FB_B(17,07) -> FPC5_T_SG(2,2,1)_FB_B(14,07)     OK       133     Up   
SF_30_03_FB_B(17,06) -> FPC5_T_SG(2,2,2)_FB_B(14,06)     OK       133     Up   
SF_30_03_FB_B(17,05) -> FPC5_T_SG(2,2,3)_FB_B(14,05)     OK       133     Up   
SF_30_03_FB_B(17,03) -> FPC5_T_SG(2,2,4)_FB_B(14,03)     OK       133     Up   
SF_30_03_FB_B(17,02) -> FPC5_T_SG(2,2,5)_FB_B(14,02)     OK       133     Up   
SF_30_03_FB_B(17,01) -> FPC5_T_SG(2,2,6)_FB_B(14,01)     OK       133     Up   
SF_30_03_FB_B(17,00) -> FPC5_T_SG(2,2,7)_FB_B(14,00)     OK       133     Up   
SF_30_04_FB_C(10,11) -> FPC2_T_SG(1,0,0)_FB_C(07,11)     OK       140     Up   
SF_30_04_FB_C(10,10) -> FPC2_T_SG(1,0,1)_FB_C(07,10)     OK       140     Up   
SF_30_04_FB_C(10,09) -> FPC2_T_SG(1,0,2)_FB_C(07,09)     OK       140     Up   
SF_30_04_FB_C(10,08) -> FPC2_T_SG(1,0,3)_FB_C(07,08)     OK       140     Up   
SF_30_04_FB_C(10,07) -> FPC2_T_SG(1,0,4)_FB_C(07,07)     OK       140     Up   
SF_30_04_FB_C(10,06) -> FPC2_T_SG(1,0,5)_FB_C(07,06)     OK       140     Up   
SF_30_04_FB_C(10,05) -> FPC2_T_SG(1,0,6)_FB_C(07,05)     OK       140     Up   
SF_30_04_FB_C(10,04) -> FPC2_T_SG(1,0,7)_FB_C(07,04)     OK       140     Up   
SF_30_05_FB_A(22,11) -> FPC6_T_SG(3,0,0)_FB_A(19,11)     OK       147     Up   
SF_30_05_FB_A(22,10) -> FPC6_T_SG(3,0,1)_FB_A(19,10)     OK       147     Up   
SF_30_05_FB_A(22,09) -> FPC6_T_SG(3,0,2)_FB_A(19,09)     OK       147     Up   
SF_30_05_FB_A(22,08) -> FPC6_T_SG(3,0,3)_FB_A(19,08)     OK       147     Up   
SF_30_05_FB_A(22,07) -> FPC6_T_SG(3,0,4)_FB_A(19,07)     OK       147     Up   
SF_30_05_FB_A(22,06) -> FPC6_T_SG(3,0,5)_FB_A(19,06)     OK       147     Up   
SF_30_05_FB_A(22,05) -> FPC6_T_SG(3,0,6)_FB_A(19,05)     OK       147     Up   
SF_30_05_FB_A(22,04) -> FPC6_T_SG(3,0,7)_FB_A(19,04)     OK       147     Up   
SF_30_06_FB_C(11,08) -> FPC3_T_SG(1,2,0)_FB_C(08,08)     OK       154     Up   
SF_30_06_FB_C(11,07) -> FPC3_T_SG(1,2,1)_FB_C(08,07)     OK       154     Up   
SF_30_06_FB_C(11,06) -> FPC3_T_SG(1,2,2)_FB_C(08,06)     OK       154     Up   
SF_30_06_FB_C(11,05) -> FPC3_T_SG(1,2,3)_FB_C(08,05)     OK       154     Up   
SF_30_06_FB_C(11,03) -> FPC3_T_SG(1,2,4)_FB_C(08,03)     OK       154     Up   
SF_30_06_FB_C(11,02) -> FPC3_T_SG(1,2,5)_FB_C(08,02)     OK       154     Up   
SF_30_06_FB_C(11,01) -> FPC3_T_SG(1,2,6)_FB_C(08,01)     OK       154     Up   
SF_30_06_FB_C(11,00) -> FPC3_T_SG(1,2,7)_FB_C(08,00)     OK       154     Up 
…

show chassis fabric topology lcc (TX Matrix Plus Router)

user@host> show chassis fabric topology lcc 0

lcc0-re0:
--------------------------------------------------------------------------

SIB0     
=========

Out-Links:
=========
LCC00_ST_SIB_L00             -> SFC0_F13_SIB_00          VCSEL    HSL2    HSL2
                                                         Status   Channel Status
================================================================================
FPC0_T_SG(0,0,0)_FB_D(04,11) -> SF_10_00_FB_D(01,11)     OK       12      Up   
FPC0_T_SG(0,0,1)_FB_D(04,10) -> SF_10_00_FB_D(01,10)     OK       12      Up   
FPC0_T_SG(0,0,2)_FB_D(04,09) -> SF_10_00_FB_D(01,09)     OK       12      Up   
FPC0_T_SG(0,0,3)_FB_D(04,08) -> SF_10_00_FB_D(01,08)     OK       12      Up   
FPC0_T_SG(0,0,4)_FB_D(04,07) -> SF_10_00_FB_D(01,07)     OK       12      Up   
FPC0_T_SG(0,0,5)_FB_D(04,06) -> SF_10_00_FB_D(01,06)     OK       12      Up   
FPC0_T_SG(0,0,6)_FB_D(04,05) -> SF_10_00_FB_D(01,05)     OK       12      Up   
FPC0_T_SG(0,0,7)_FB_D(04,04) -> SF_10_00_FB_D(01,04)     OK       12      Up   
FPC0_B_SG(0,1,0)_FB_D(03,07) -> SF_10_10_FB_D(00,07)     OK       15      Up   
FPC0_B_SG(0,1,1)_FB_D(03,06) -> SF_10_10_FB_D(00,06)     OK       15      Up   
FPC0_B_SG(0,1,2)_FB_D(03,05) -> SF_10_10_FB_D(00,05)     OK       15      Up   
FPC0_B_SG(0,1,3)_FB_D(03,04) -> SF_10_10_FB_D(00,04)     OK       15      Up   
FPC0_B_SG(0,1,4)_FB_D(03,03) -> SF_10_10_FB_D(00,03)     OK       15      Up   
FPC0_B_SG(0,1,5)_FB_D(03,02) -> SF_10_10_FB_D(00,02)     OK       15      Up   
FPC0_B_SG(0,1,6)_FB_D(03,01) -> SF_10_10_FB_D(00,01)     OK       15      Up   
FPC0_B_SG(0,1,7)_FB_D(03,00) -> SF_10_10_FB_D(00,00)     OK       15      Up   
FPC1_T_SG(0,2,0)_FB_D(05,08) -> SF_10_02_FB_D(02,08)     OK       18      Up   
FPC1_T_SG(0,2,1)_FB_D(05,07) -> SF_10_02_FB_D(02,07)     OK       18      Up   
FPC1_T_SG(0,2,2)_FB_D(05,06) -> SF_10_02_FB_D(02,06)     OK       18      Up   
FPC1_T_SG(0,2,3)_FB_D(05,05) -> SF_10_02_FB_D(02,05)     OK       18      Up   
FPC1_T_SG(0,2,4)_FB_D(05,03) -> SF_10_02_FB_D(02,03)     OK       18      Up   
FPC1_T_SG(0,2,5)_FB_D(05,02) -> SF_10_02_FB_D(02,02)     OK       18      Up   
FPC1_T_SG(0,2,6)_FB_D(05,01) -> SF_10_02_FB_D(02,01)     OK       18      Up   
FPC1_T_SG(0,2,7)_FB_D(05,00) -> SF_10_02_FB_D(02,00)     OK       18      Up   
FPC1_B_SG(0,3,0)_FB_D(04,03) -> SF_10_11_FB_D(01,03)     OK       21      Up   
FPC1_B_SG(0,3,1)_FB_D(04,02) -> SF_10_11_FB_D(01,02)     OK       21      Up   
FPC1_B_SG(0,3,2)_FB_D(04,01) -> SF_10_11_FB_D(01,01)     OK       21      Up   
FPC1_B_SG(0,3,3)_FB_D(04,00) -> SF_10_11_FB_D(01,00)     OK       21      Up   
FPC1_B_SG(0,3,4)_FB_D(03,11) -> SF_10_11_FB_D(00,11)     OK       21      Up   
FPC1_B_SG(0,3,5)_FB_D(03,10) -> SF_10_11_FB_D(00,10)     OK       21      Up   
FPC1_B_SG(0,3,6)_FB_D(03,09) -> SF_10_11_FB_D(00,09)     OK       21      Up   
FPC1_B_SG(0,3,7)_FB_D(03,08) -> SF_10_11_FB_D(00,08)     OK       21      Up   
FPC2_T_SG(1,0,0)_FB_C(10,11) -> SF_10_04_FB_C(07,11)     OK       12      Up   
FPC2_T_SG(1,0,1)_FB_C(10,10) -> SF_10_04_FB_C(07,10)     OK       12      Up   
FPC2_T_SG(1,0,2)_FB_C(10,09) -> SF_10_04_FB_C(07,09)     OK       12      Up   
FPC2_T_SG(1,0,3)_FB_C(10,08) -> SF_10_04_FB_C(07,08)     OK       12      Up   
FPC2_T_SG(1,0,4)_FB_C(10,07) -> SF_10_04_FB_C(07,07)     OK       12      Up   
FPC2_T_SG(1,0,5)_FB_C(10,06) -> SF_10_04_FB_C(07,06)     OK       12      Up   
FPC2_T_SG(1,0,6)_FB_C(10,05) -> SF_10_04_FB_C(07,05)     OK       12      Up   
FPC2_T_SG(1,0,7)_FB_C(10,04) -> SF_10_04_FB_C(07,04)     OK       12      Up   
FPC2_B_SG(1,1,0)_FB_C(09,07) -> SF_10_14_FB_C(06,07)     OK       15      Up   
FPC2_B_SG(1,1,1)_FB_C(09,06) -> SF_10_14_FB_C(06,06)     OK       15      Up   
FPC2_B_SG(1,1,2)_FB_C(09,05) -> SF_10_14_FB_C(06,05)     OK       15      Up   
FPC2_B_SG(1,1,3)_FB_C(09,04) -> SF_10_14_FB_C(06,04)     OK       15      Up   
FPC2_B_SG(1,1,4)_FB_C(09,03) -> SF_10_14_FB_C(06,03)     OK       15      Up   
FPC2_B_SG(1,1,5)_FB_C(09,02) -> SF_10_14_FB_C(06,02)     OK       15      Up   
FPC2_B_SG(1,1,6)_FB_C(09,01) -> SF_10_14_FB_C(06,01)     OK       15      Up   
FPC2_B_SG(1,1,7)_FB_C(09,00) -> SF_10_14_FB_C(06,00)     OK       15      Up   
FPC3_T_SG(1,2,0)_FB_C(11,08) -> SF_10_06_FB_C(08,08)     OK       18      Up   
FPC3_T_SG(1,2,1)_FB_C(11,07) -> SF_10_06_FB_C(08,07)     OK       18      Up   
FPC3_T_SG(1,2,2)_FB_C(11,06) -> SF_10_06_FB_C(08,06)     OK       18      Up   
FPC3_T_SG(1,2,3)_FB_C(11,05) -> SF_10_06_FB_C(08,05)     OK       18      Up   
FPC3_T_SG(1,2,4)_FB_C(11,03) -> SF_10_06_FB_C(08,03)     OK       18      Up   
FPC3_T_SG(1,2,5)_FB_C(11,02) -> SF_10_06_FB_C(08,02)     OK       18      Up   
FPC3_T_SG(1,2,6)_FB_C(11,01) -> SF_10_06_FB_C(08,01)     OK       18      Up   
...

show chassis fabric topology (T4000 Core Router)

user@host> show chassis fabric topology 0

 fchip (mode)
          In-links               State             Out-links              State
--------------------------------------------------------------------------------
 
SIB0 :
---------
 
Onboard Links
-------------
SIB0_XF1,14_0->SIB0_XF,00_0      Up      SIB0_XF,00_0->SIB0_XF1,14_0      Up   
SIB0_XF,00_0->SIB0_XF1,14_0      Up      SIB0_XF1,14_0->SIB0_XF,00_0      Up   
SIB0_XF1,13_0->SIB0_XF,01_0      Up      SIB0_XF,01_0->SIB0_XF1,13_0      Up   
SIB0_XF,01_0->SIB0_XF1,13_0      Up      SIB0_XF1,13_0->SIB0_XF,01_0      Up   
SIB0_XF1,12_0->SIB0_XF,02_0      Up      SIB0_XF,02_0->SIB0_XF1,12_0      Up   
SIB0_XF,02_0->SIB0_XF1,12_0      Up      SIB0_XF1,12_0->SIB0_XF,02_0      Up   
SIB0_XF1,11_0->SIB0_XF,03_0      Up      SIB0_XF,03_0->SIB0_XF1,11_0      Up   
SIB0_XF,03_0->SIB0_XF1,11_0      Up      SIB0_XF1,11_0->SIB0_XF,03_0      Up   
SIB0_XF1,10_0->SIB0_XF,04_0      Up      SIB0_XF,04_0->SIB0_XF1,10_0      Up   
SIB0_XF,04_0->SIB0_XF1,10_0      Up      SIB0_XF1,10_0->SIB0_XF,04_0      Up   
SIB0_XF1,09_0->SIB0_XF,05_0      Up      SIB0_XF,05_0->SIB0_XF1,09_0      Up   
SIB0_XF,05_0->SIB0_XF1,09_0      Up      SIB0_XF1,09_0->SIB0_XF,05_0      Up   
SIB0_XF2,14_0->SIB0_XF,06_0      Up      SIB0_XF,06_0->SIB0_XF2,14_0      Up   
SIB0_XF,06_0->SIB0_XF2,14_0      Up      SIB0_XF2,14_0->SIB0_XF,06_0      Up   
SIB0_XF2,13_0->SIB0_XF,07_0      Up      SIB0_XF,07_0->SIB0_XF2,13_0      Up   
SIB0_XF,07_0->SIB0_XF2,13_0      Up      SIB0_XF2,13_0->SIB0_XF,07_0      Up   
SIB0_XF2,12_0->SIB0_XF,08_0      Up      SIB0_XF,08_0->SIB0_XF2,12_0      Up   
SIB0_XF,08_0->SIB0_XF2,12_0      Up      SIB0_XF2,12_0->SIB0_XF,08_0      Up   
SIB0_XF2,11_0->SIB0_XF,09_0      Up      SIB0_XF,09_0->SIB0_XF2,11_0      Up   
SIB0_XF,09_0->SIB0_XF2,11_0      Up      SIB0_XF2,11_0->SIB0_XF,09_0      Up   
SIB0_XF2,10_0->SIB0_XF,10_0      Up      SIB0_XF,10_0->SIB0_XF2,10_0      Up   
SIB0_XF,10_0->SIB0_XF2,10_0      Up      SIB0_XF2,10_0->SIB0_XF,10_0      Up   
SIB0_XF2,09_0->SIB0_XF,11_0      Up      SIB0_XF,11_0->SIB0_XF2,09_0      Up   
SIB0_XF,11_0->SIB0_XF2,09_0      Up      SIB0_XF2,09_0->SIB0_XF,11_0      Up   
SIB0_XF3,13_0->SIB0_XF,12_0      Up      SIB0_XF,12_0->SIB0_XF3,13_0      Up   
SIB0_XF,12_0->SIB0_XF3,13_0      Up      SIB0_XF3,13_0->SIB0_XF,12_0      Up   
SIB0_XF3,12_0->SIB0_XF,13_0      Up      SIB0_XF,13_0->SIB0_XF3,12_0      Up   
SIB0_XF,13_0->SIB0_XF3,12_0      Up      SIB0_XF3,12_0->SIB0_XF,13_0      Up   
SIB0_XF3,11_0->SIB0_XF,14_0      Up      SIB0_XF,14_0->SIB0_XF3,11_0      Up   
SIB0_XF,14_0->SIB0_XF3,11_0      Up      SIB0_XF3,11_0->SIB0_XF,14_0      Up   
SIB0_XF3,10_0->SIB0_XF,15_0      Up      SIB0_XF,15_0->SIB0_XF3,10_0      Up   
SIB0_XF,15_0->SIB0_XF3,10_0      Up      SIB0_XF3,10_0->SIB0_XF,15_0      Up   
 
PFE Links
---------------
FPC2PFE0->SIB0_XF1,05_0          Up      SIB0_XF1,05_0->FPC2PFE0          Up   
FPC3PFE0->SIB0_XF2,15_0          Up      SIB0_XF2,15_0->FPC3PFE0          Up   
FPC5PFE0->SIB0_XF2,05_0          Up      SIB0_XF2,05_0->FPC5PFE0          Up   
FPC5PFE1->SIB0_XF2,07_0          Up      SIB0_XF2,07_0->FPC5PFE1          Up   
FPC6PFE0->SIB0_XF3,01_0          Up      SIB0_XF3,01_0->FPC6PFE0          Up   
FPC6PFE0->SIB0_XF3,01_1          Up      SIB0_XF3,01_1->FPC6PFE0          Up   
FPC6PFE0->SIB0_XF3,02_0          Up      SIB0_XF3,02_0->FPC6PFE0          Up   
FPC6PFE1->SIB0_XF3,03_0          Up      SIB0_XF3,03_0->FPC6PFE1          Up   
FPC6PFE1->SIB0_XF3,03_1          Up      SIB0_XF3,03_1->FPC6PFE1          Up   
FPC6PFE1->SIB0_XF3,02_1          Up      SIB0_XF3,02_1->FPC6PFE1          Up

show chassis fabric topology (PTX Series Packet Transport Switches)

user@host> show chassis fabric topology

In-link  : FPC# FE# TQ# (TQ-TX sub-chnl #) ->
            SIB# TF#_FCORE# (TF-RX port#, TF-RX sub-chn#, TF-RX inst#)
 
 Out-link : SIB# TF#_FCORE# (TF-TX port#, TF-TX sub-chn#, TF-TX inst#) ->
            FPC# FE# TQ# (TQ-RX sub-chnl #)
(6, 4, 06) in FPC02FE0TQ0(02)->S01F0_0(6,4,06) will be TF Rx Port 6, TF CCL Rx Sub-Channel 4, TF CCL Rx Instance 6.
(2, 7, 10) in S01F0_0(2,7,10)->FPC02FE0TQ0(02) will be TF-Tx Port 2, TF CCL Tx Sub-channel 7, TF CCL Tx Instance 10.
SIB 0 FCHIP 0 FCORE 0 :
-----------------------
          In-links               State             Out-links              State
--------------------------------------------------------------------------------
FPC00FE0TQ0(00)->S00F0_0(7,4,07) OK      S00F0_0(3,7,11)->FPC00FE0TQ0(00) OK   
FPC00FE1TQ1(00)->S00F0_0(7,6,07) OK      S00F0_0(3,5,11)->FPC00FE1TQ1(00) OK   
FPC00FE2TQ2(00)->S00F0_0(7,5,07) OK      S00F0_0(3,6,11)->FPC00FE2TQ2(00) OK   
FPC00FE3TQ3(00)->S00F0_0(7,7,07) OK      S00F0_0(3,4,11)->FPC00FE3TQ3(00) OK   
FPC01FE0TQ0(00)->S00F0_0(7,0,07) OK      S00F0_0(3,3,11)->FPC01FE0TQ0(00) OK   
FPC01FE1TQ1(00)->S00F0_0(7,1,07) OK      S00F0_0(3,1,11)->FPC01FE1TQ1(00) OK   
FPC01FE2TQ2(00)->S00F0_0(7,2,07) OK      S00F0_0(3,2,11)->FPC01FE2TQ2(00) Error
FPC01FE3TQ3(00)->S00F0_0(7,3,07) OK      S00F0_0(3,0,11)->FPC01FE3TQ3(00) OK   
FPC02FE0TQ0(00)->S00F0_0(6,4,06) OK      S00F0_0(2,7,10)->FPC02FE0TQ0(00) OK   
FPC02FE1TQ1(00)->S00F0_0(6,5,06) OK      S00F0_0(2,5,10)->FPC02FE1TQ1(00) OK   
FPC02FE2TQ2(00)->S00F0_0(6,6,06) OK      S00F0_0(2,6,10)->FPC02FE2TQ2(00) OK   
FPC02FE3TQ3(00)->S00F0_0(6,7,06) OK      S00F0_0(2,4,10)->FPC02FE3TQ3(00) OK   
FPC03FE0TQ0(00)->S00F0_0(6,0,06) Down    S00F0_0(2,3,10)->FPC03FE0TQ0(00) Down 
FPC03FE1TQ1(00)->S00F0_0(6,1,06) Down    S00F0_0(2,0,10)->FPC03FE1TQ1(00) Down 
FPC03FE2TQ2(00)->S00F0_0(6,2,06) Down    S00F0_0(2,2,10)->FPC03FE2TQ2(00) Down 
FPC03FE3TQ3(00)->S00F0_0(6,3,06) Down    S00F0_0(2,1,10)->FPC03FE3TQ3(00) Down 
FPC04FE0TQ0(00)->S00F0_0(5,4,05) OK      S00F0_0(1,7,09)->FPC04FE0TQ0(00) OK   
FPC04FE1TQ1(00)->S00F0_0(5,5,05) OK      S00F0_0(1,6,09)->FPC04FE1TQ1(00) OK   
FPC04FE2TQ2(00)->S00F0_0(5,6,05) OK      S00F0_0(1,4,09)->FPC04FE2TQ2(00) OK   
FPC04FE3TQ3(00)->S00F0_0(5,7,05) OK      S00F0_0(1,5,09)->FPC04FE3TQ3(00) OK   
FPC05FE0TQ0(00)->S00F0_0(5,0,05) OK      S00F0_0(1,3,09)->FPC05FE0TQ0(00) OK   
FPC05FE1TQ1(00)->S00F0_0(5,1,05) OK      S00F0_0(1,0,09)->FPC05FE1TQ1(00) OK   
FPC05FE2TQ2(00)->S00F0_0(5,2,05) OK      S00F0_0(1,2,09)->FPC05FE2TQ2(00) OK   
FPC05FE3TQ3(00)->S00F0_0(5,3,05) OK      S00F0_0(1,1,09)->FPC05FE3TQ3(00) OK   
FPC06FE0TQ0(00)->S00F0_0(4,4,04) Down    S00F0_0(0,7,08)->FPC06FE0TQ0(00) Down 
FPC06FE1TQ1(00)->S00F0_0(4,5,04) Down    S00F0_0(0,5,08)->FPC06FE1TQ1(00) Down 
FPC06FE2TQ2(00)->S00F0_0(4,6,04) Down    S00F0_0(0,6,08)->FPC06FE2TQ2(00) Down 
FPC06FE3TQ3(00)->S00F0_0(4,7,04) Down    S00F0_0(0,4,08)->FPC06FE3TQ3(00) Down 
FPC07FE0TQ0(00)->S00F0_0(4,2,04) Down    S00F0_0(0,3,08)->FPC07FE0TQ0(00) Down 
FPC07FE1TQ1(00)->S00F0_0(4,0,04) Down    S00F0_0(0,0,08)->FPC07FE1TQ1(00) Down 
FPC07FE2TQ2(00)->S00F0_0(4,1,04) Down    S00F0_0(0,1,08)->FPC07FE2TQ2(00) Down 
FPC07FE3TQ3(00)->S00F0_0(4,3,04) Down    S00F0_0(0,2,08)->FPC07FE3TQ3(00) Down 
 
SIB 0 FCHIP 0 FCORE 1 :
-----------------------
          In-links               State             Out-links              State
--------------------------------------------------------------------------------
FPC00FE0TQ0(01)->S00F0_1(3,4,11) OK      S00F0_1(7,6,07)->FPC00FE0TQ0(01) OK   
FPC00FE1TQ1(01)->S00F0_1(3,5,11) OK      S00F0_1(7,4,07)->FPC00FE1TQ1(01) OK   
FPC00FE2TQ2(01)->S00F0_1(3,6,11) OK      S00F0_1(7,7,07)->FPC00FE2TQ2(01) OK   
FPC00FE3TQ3(01)->S00F0_1(3,7,11) OK      S00F0_1(7,5,07)->FPC00FE3TQ3(01) OK   
FPC01FE0TQ0(01)->S00F0_1(3,0,11) OK      S00F0_1(7,2,07)->FPC01FE0TQ0(01) OK   
FPC01FE1TQ1(01)->S00F0_1(3,1,11) OK      S00F0_1(7,0,07)->FPC01FE1TQ1(01) OK   
FPC01FE2TQ2(01)->S00F0_1(3,2,11) OK      S00F0_1(7,3,07)->FPC01FE2TQ2(01) OK   
FPC01FE3TQ3(01)->S00F0_1(3,3,11) OK      S00F0_1(7,1,07)->FPC01FE3TQ3(01) OK   
FPC02FE0TQ0(01)->S00F0_1(2,4,10) OK      S00F0_1(6,5,06)->FPC02FE0TQ0(01) OK   
FPC02FE1TQ1(01)->S00F0_1(2,5,10) OK      S00F0_1(6,4,06)->FPC02FE1TQ1(01) OK   
FPC02FE2TQ2(01)->S00F0_1(2,6,10) OK      S00F0_1(6,7,06)->FPC02FE2TQ2(01) OK   
FPC02FE3TQ3(01)->S00F0_1(2,7,10) OK      S00F0_1(6,6,06)->FPC02FE3TQ3(01) OK   
FPC03FE0TQ0(01)->S00F0_1(2,0,10) Down    S00F0_1(6,1,06)->FPC03FE0TQ0(01) Down 
FPC03FE1TQ1(01)->S00F0_1(2,1,10) Down    S00F0_1(6,0,06)->FPC03FE1TQ1(01) Down 
FPC03FE2TQ2(01)->S00F0_1(2,2,10) Down    S00F0_1(6,3,06)->FPC03FE2TQ2(01) Down 
FPC03FE3TQ3(01)->S00F0_1(2,3,10) Down    S00F0_1(6,2,06)->FPC03FE3TQ3(01) Down 
FPC04FE0TQ0(01)->S00F0_1(1,4,09) OK      S00F0_1(5,5,05)->FPC04FE0TQ0(01) OK   
FPC04FE1TQ1(01)->S00F0_1(1,5,09) OK      S00F0_1(5,4,05)->FPC04FE1TQ1(01) OK   
FPC04FE2TQ2(01)->S00F0_1(1,6,09) OK      S00F0_1(5,7,05)->FPC04FE2TQ2(01) OK   
FPC04FE3TQ3(01)->S00F0_1(1,7,09) OK      S00F0_1(5,6,05)->FPC04FE3TQ3(01) OK   
FPC05FE0TQ0(01)->S00F0_1(1,0,09) OK      S00F0_1(5,1,05)->FPC05FE0TQ0(01) OK   
FPC05FE1TQ1(01)->S00F0_1(1,1,09) OK      S00F0_1(5,0,05)->FPC05FE1TQ1(01) OK   
FPC05FE2TQ2(01)->S00F0_1(1,2,09) OK      S00F0_1(5,3,05)->FPC05FE2TQ2(01) OK   
FPC05FE3TQ3(01)->S00F0_1(1,3,09) OK      S00F0_1(5,2,05)->FPC05FE3TQ3(01) OK   
FPC06FE0TQ0(01)->S00F0_1(0,4,08) Down    S00F0_1(4,7,04)->FPC06FE0TQ0(01) Down 
FPC06FE1TQ1(01)->S00F0_1(0,5,08) Down    S00F0_1(4,0,04)->FPC06FE1TQ1(01) Down 
FPC06FE2TQ2(01)->S00F0_1(0,6,08) Down    S00F0_1(4,6,04)->FPC06FE2TQ2(01) Down 
FPC06FE3TQ3(01)->S00F0_1(0,7,08) Down    S00F0_1(4,1,04)->FPC06FE3TQ3(01) Down 
FPC07FE0TQ0(01)->S00F0_1(0,0,08) Down    S00F0_1(4,3,04)->FPC07FE0TQ0(01) Down 
FPC07FE1TQ1(01)->S00F0_1(0,1,08) Down    S00F0_1(4,4,04)->FPC07FE1TQ1(01) Down 
FPC07FE2TQ2(01)->S00F0_1(0,2,08) Down    S00F0_1(4,2,04)->FPC07FE2TQ2(01) Down 
FPC07FE3TQ3(01)->S00F0_1(0,3,08) Down    S00F0_1(4,5,04)->FPC07FE3TQ3(01) Down 
 
SIB 1 FCHIP 0 FCORE 0 :
-----------------------
          In-links               State             Out-links              State
--------------------------------------------------------------------------------
FPC00FE0TQ0(02)->S01F0_0(7,4,07) Error   S01F0_0(3,7,11)->FPC00FE0TQ0(02) Down 
FPC00FE1TQ1(02)->S01F0_0(7,6,07) OK      S01F0_0(3,5,11)->FPC00FE1TQ1(02) OK   
FPC00FE2TQ2(02)->S01F0_0(7,5,07) OK      S01F0_0(3,6,11)->FPC00FE2TQ2(02) OK   
FPC00FE3TQ3(02)->S01F0_0(7,7,07) OK      S01F0_0(3,4,11)->FPC00FE3TQ3(02) OK   
FPC01FE0TQ0(02)->S01F0_0(7,0,07) OK      S01F0_0(3,3,11)->FPC01FE0TQ0(02) OK   
FPC01FE1TQ1(02)->S01F0_0(7,1,07) OK      S01F0_0(3,1,11)->FPC01FE1TQ1(02) OK   
FPC01FE2TQ2(02)->S01F0_0(7,2,07) OK      S01F0_0(3,2,11)->FPC01FE2TQ2(02) OK   
FPC01FE3TQ3(02)->S01F0_0(7,3,07) OK      S01F0_0(3,0,11)->FPC01FE3TQ3(02) OK   
FPC02FE0TQ0(02)->S01F0_0(6,4,06) OK      S01F0_0(2,7,10)->FPC02FE0TQ0(02) OK   
FPC02FE1TQ1(02)->S01F0_0(6,5,06) OK      S01F0_0(2,5,10)->FPC02FE1TQ1(02) OK   
FPC02FE2TQ2(02)->S01F0_0(6,6,06) OK      S01F0_0(2,6,10)->FPC02FE2TQ2(02) OK   
FPC02FE3TQ3(02)->S01F0_0(6,7,06) OK      S01F0_0(2,4,10)->FPC02FE3TQ3(02) OK   
FPC03FE0TQ0(02)->S01F0_0(6,0,06) Down    S01F0_0(2,3,10)->FPC03FE0TQ0(02) Down 
FPC03FE1TQ1(02)->S01F0_0(6,1,06) Down    S01F0_0(2,0,10)->FPC03FE1TQ1(02) Down 
FPC03FE2TQ2(02)->S01F0_0(6,2,06) Down    S01F0_0(2,2,10)->FPC03FE2TQ2(02) Down 
FPC03FE3TQ3(02)->S01F0_0(6,3,06) Down    S01F0_0(2,1,10)->FPC03FE3TQ3(02) Down 
FPC04FE0TQ0(02)->S01F0_0(5,4,05) OK      S01F0_0(1,7,09)->FPC04FE0TQ0(02) OK   
FPC04FE1TQ1(02)->S01F0_0(5,5,05) OK      S01F0_0(1,6,09)->FPC04FE1TQ1(02) OK   
FPC04FE2TQ2(02)->S01F0_0(5,6,05) OK      S01F0_0(1,4,09)->FPC04FE2TQ2(02) OK   
FPC04FE3TQ3(02)->S01F0_0(5,7,05) OK      S01F0_0(1,5,09)->FPC04FE3TQ3(02) OK   
FPC05FE0TQ0(02)->S01F0_0(5,0,05) OK      S01F0_0(1,3,09)->FPC05FE0TQ0(02) OK   
FPC05FE1TQ1(02)->S01F0_0(5,1,05) OK      S01F0_0(1,0,09)->FPC05FE1TQ1(02) OK   
FPC05FE2TQ2(02)->S01F0_0(5,2,05) OK      S01F0_0(1,2,09)->FPC05FE2TQ2(02) OK   
FPC05FE3TQ3(02)->S01F0_0(5,3,05) OK      S01F0_0(1,1,09)->FPC05FE3TQ3(02) OK   
FPC06FE0TQ0(02)->S01F0_0(4,4,04) Down    S01F0_0(0,7,08)->FPC06FE0TQ0(02) Down 
FPC06FE1TQ1(02)->S01F0_0(4,5,04) Down    S01F0_0(0,5,08)->FPC06FE1TQ1(02) Down 
FPC06FE2TQ2(02)->S01F0_0(4,6,04) Down    S01F0_0(0,6,08)->FPC06FE2TQ2(02) Down 
FPC06FE3TQ3(02)->S01F0_0(4,7,04) Down    S01F0_0(0,4,08)->FPC06FE3TQ3(02) Down 
FPC07FE0TQ0(02)->S01F0_0(4,2,04) Down    S01F0_0(0,3,08)->FPC07FE0TQ0(02) Down 
FPC07FE1TQ1(02)->S01F0_0(4,0,04) Down    S01F0_0(0,0,08)->FPC07FE1TQ1(02) Down 
FPC07FE2TQ2(02)->S01F0_0(4,1,04) Down    S01F0_0(0,1,08)->FPC07FE2TQ2(02) Down 
FPC07FE3TQ3(02)->S01F0_0(4,3,04) Down    S01F0_0(0,2,08)->FPC07FE3TQ3(02) Down 
 
SIB 1 FCHIP 0 FCORE 1 :
-----------------------
          In-links               State             Out-links              State
--------------------------------------------------------------------------------
FPC00FE0TQ0(03)->S01F0_1(3,4,11) OK      S01F0_1(7,6,07)->FPC00FE0TQ0(03) OK   
FPC00FE1TQ1(03)->S01F0_1(3,5,11) OK      S01F0_1(7,4,07)->FPC00FE1TQ1(03) OK   
FPC00FE2TQ2(03)->S01F0_1(3,6,11) OK      S01F0_1(7,7,07)->FPC00FE2TQ2(03) OK   
FPC00FE3TQ3(03)->S01F0_1(3,7,11) OK      S01F0_1(7,5,07)->FPC00FE3TQ3(03) OK   
FPC01FE0TQ0(03)->S01F0_1(3,0,11) OK      S01F0_1(7,2,07)->FPC01FE0TQ0(03) OK   
FPC01FE1TQ1(03)->S01F0_1(3,1,11) OK      S01F0_1(7,0,07)->FPC01FE1TQ1(03) OK   
FPC01FE2TQ2(03)->S01F0_1(3,2,11) OK      S01F0_1(7,3,07)->FPC01FE2TQ2(03) OK   
FPC01FE3TQ3(03)->S01F0_1(3,3,11) OK      S01F0_1(7,1,07)->FPC01FE3TQ3(03) OK   
FPC02FE0TQ0(03)->S01F0_1(2,4,10) OK      S01F0_1(6,5,06)->FPC02FE0TQ0(03) OK   
FPC02FE1TQ1(03)->S01F0_1(2,5,10) OK      S01F0_1(6,4,06)->FPC02FE1TQ1(03) OK   
FPC02FE2TQ2(03)->S01F0_1(2,6,10) OK      S01F0_1(6,7,06)->FPC02FE2TQ2(03) OK   
FPC02FE3TQ3(03)->S01F0_1(2,7,10) OK      S01F0_1(6,6,06)->FPC02FE3TQ3(03) OK   
FPC03FE0TQ0(03)->S01F0_1(2,0,10) Down    S01F0_1(6,1,06)->FPC03FE0TQ0(03) Down 
FPC03FE1TQ1(03)->S01F0_1(2,1,10) Down    S01F0_1(6,0,06)->FPC03FE1TQ1(03) Down 
FPC03FE2TQ2(03)->S01F0_1(2,2,10) Down    S01F0_1(6,3,06)->FPC03FE2TQ2(03) Down 
FPC03FE3TQ3(03)->S01F0_1(2,3,10) Down    S01F0_1(6,2,06)->FPC03FE3TQ3(03) Down 
FPC04FE0TQ0(03)->S01F0_1(1,4,09) OK      S01F0_1(5,5,05)->FPC04FE0TQ0(03) OK   
FPC04FE1TQ1(03)->S01F0_1(1,5,09) OK      S01F0_1(5,4,05)->FPC04FE1TQ1(03) OK   
FPC04FE2TQ2(03)->S01F0_1(1,6,09) OK      S01F0_1(5,7,05)->FPC04FE2TQ2(03) OK   
FPC04FE3TQ3(03)->S01F0_1(1,7,09) OK      S01F0_1(5,6,05)->FPC04FE3TQ3(03) OK   
FPC05FE0TQ0(03)->S01F0_1(1,0,09) OK      S01F0_1(5,1,05)->FPC05FE0TQ0(03) OK   
FPC05FE1TQ1(03)->S01F0_1(1,1,09) OK      S01F0_1(5,0,05)->FPC05FE1TQ1(03) OK   
FPC05FE2TQ2(03)->S01F0_1(1,2,09) OK      S01F0_1(5,3,05)->FPC05FE2TQ2(03) OK   
FPC05FE3TQ3(03)->S01F0_1(1,3,09) OK      S01F0_1(5,2,05)->FPC05FE3TQ3(03) OK   
FPC06FE0TQ0(03)->S01F0_1(0,4,08) Down    S01F0_1(4,7,04)->FPC06FE0TQ0(03) Down 
FPC06FE1TQ1(03)->S01F0_1(0,5,08) Down    S01F0_1(4,0,04)->FPC06FE1TQ1(03) Down 
FPC06FE2TQ2(03)->S01F0_1(0,6,08) Down    S01F0_1(4,6,04)->FPC06FE2TQ2(03) Down 
FPC06FE3TQ3(03)->S01F0_1(0,7,08) Down    S01F0_1(4,1,04)->FPC06FE3TQ3(03) Down 
FPC07FE0TQ0(03)->S01F0_1(0,0,08) Down    S01F0_1(4,3,04)->FPC07FE0TQ0(03) Down 
FPC07FE1TQ1(03)->S01F0_1(0,1,08) Down    S01F0_1(4,4,04)->FPC07FE1TQ1(03) Down 
FPC07FE2TQ2(03)->S01F0_1(0,2,08) Down    S01F0_1(4,2,04)->FPC07FE2TQ2(03) Down 
FPC07FE3TQ3(03)->S01F0_1(0,3,08) Down    S01F0_1(4,5,04)->FPC07FE3TQ3(03) Down

TechLibrary

Related Documentation

show chassis fabric topology

Syntax

Syntax (TX Matrix Router)

Syntax (TX Matrix Plus Router)

Syntax (T4000 Core Router)

Syntax (PTX Series Packet Transport Switches)

Release Information

Description

Options

Required Privilege Level

Related Documentation

List of Sample Output

Output Fields

Sample Output

Published: 2013-01-30