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Configuring Channelized OC48/STM16 IQE Interfaces (SONET Mode)

 

Configuring OC12 Interfaces

You can configure up to four OC12 interfaces on a 1-port Channelized OC48/STM16 IQE PIC.

To configure an OC12 interface:

  1. In the configuration mode go to the [edit interfaces coc48-fpc/pic/port] hierarchy level:
  2. Include the partition, oc-slice, and interface-type statements and specify so interface type.

The partition number is the sublevel interface partition index. For SONET/SDH interfaces, the partition number does not correlate with bandwidth size. For OC12 interfaces, the partition number can be from 1 through 4.

Note

For channelized OC48 IQE interfaces, channel numbering begins with 1 (:1).

The OC-slice range is the range of SONET/SDH slices. For SONET/SDH interfaces, the OC-slice range specifies the bandwidth size required for the interface type you are configuring. OC12 interfaces must occupy 12 consecutive OC slices per interface, in one of the following forms:

  • 1–12

  • 13–24

  • 25–26

  • 37–48

By contrast, the T3 and OC1 interfaces each occupy one OC slice per interface and OC3 interfaces occupy three slices per interface.

The interface type is the channelized interface type or data channel you are creating. For channelized OC48 IQE interfaces, the interface type can be so.

Example: Configuring OC12 Interfaces

Configure an OC12 interface, using partition 1 and OC slices 1 through 12. .

This configuration creates interface so-1/1/0:1

Configuring OC3 Interfaces

To configure an OC3 interface:

  1. In the configuration mode go to the [edit interfaces coc48-fpc/pic/port] hierarchy level:
  2. Include the partition, oc-slice, and interface-type statements and specify so interface type.

The partition number is the sublevel interface partition index. For SONET/SDH interfaces, the partition number does not correlate with bandwidth size. For OC3 interfaces, the partition number can be from 1 through 16.

Note

For channelized OC48 IQE interfaces, channel numbering begins with 1 (:1).

The OC-slice range is the range of SONET/SDH slices. For SONET/SDH interfaces, the OC-slice range specifies the bandwidth size required for the interface type you are configuring. OC3 interfaces must occupy three consecutive OC slices per interface, in one of the following forms:

  • 1–3

  • 4–6

  • 7–9

  • 10–12

  • and so on (in groups of 3), up to 48

By contrast, the T3 and OC1 interfaces each occupy one OC slice per interface.

The interface type is the channelized interface type or data channel you are creating. For channelized OC48 IQE interfaces, the interface type can be so.

Example: Configuring OC3 Interfaces

Configure an OC3 interface, using partition 1 and OC slices 4 through 6.

This configuration creates interface so-1/1/0:1

Configuring T3 Interfaces

Channelized OC48/STM16 IQE interfaces in M Series, MX Series, and T Series routers reserve channels 0 through 3 of each OC12 space for STS3C SONET channels.

When you configure E3 or T3 channels in OC12 spaces on the described PICs, the Junos OS allocates them starting from channel 4 because channels 0 through 3 are reserved for four STS3c SONET channels. Channel numbers are allocated sequentially in the following order: 4, 5, 6, 7, 8, 9, 11, 0, 1, 2, 3.

Only after channels 4 through 11 of the OC12 space are exhausted (all 4 through 11 configured) for E3 or T3 channels will the Junos OS then allocate channel 0 through 3 space for further E3 or T3 channels; thereby using up the 0 through 3 space previously reserved for four STS3c SONET channels.

If a subsequent reconfiguration of this OC12 space occurs, where you try to replace channels 4 through 6 or 7 through 9 with an OC3 SONET channel; the configuration fails because the channel 0 through 3 space is already occupied by the last E3 or T3 channels configured. This causes a failure in channel allocation and the Device Control Daemon (DCD) keeps retrying forever to configure the channel allocation on the interface. The only resolution is to reconfigure the last configured E3/T3 channels with OC3 channels, to free channels 0 through 3.

To configure a T3 interface on an OC48/STM16 IQE PIC:

  1. In the configuration mode go to the [edit interfaces coc48-fpc/pic/port] hierarchy level:
  2. Include the partition, oc-slice, and interface-type statements and specify coc1 interface type.

    This configuration creates interface coc1-fpc/pic/port:channel.

  3. Go to [edit interfaces coc1-fpc/pic/port:channel] hierarchy level.
  4. Include the no-partition interface-type statement specifying the t3 interface type.

    This configuration creates interface t3-fpc/pic/port:channel.

The partition number is the sublevel interface partition index and is correlated with the channel number. For channelized OC1 interfaces, the partition number can be from 1 through 48. For channelized OC48/STM16 IQE interfaces, channel numbering begins with 1 (:1).

The OC-slice range is the range of SONET/SDH slices. For SONET/SDH interfaces, the OC-slice range specifies the bandwidth size required for the interface type you are configuring. For channelized OC1 interfaces, the OC slice can be from 1 through 12. You can configure only one OC slice per channelized OC1 interface.

The interface type is the channelized interface type or clear channel you are creating. For channelized OC48 interfaces, type can be so or coc1.

Example: Configuring T3 Interfaces

Configure a T3 interface using partition 3 and OC slice 3.

This configuration creates interface t3-1/1/0:3

Configuring T1 Interfaces

To configure T1 interfaces on a Channelized OC48 IQE PIC, perform the following tasks:

  1. In the configuration mode go to the [edit interfaces coc48-fpc/pic/port] hierarchy level.
  2. Partition the channelized OC48 IQE interface into channelized OC1 interfaces by including the partition, oc-slice, and interface-type statements and specify coc1 interface type.
  3. If your network equipment uses VT mapping, in the configuration mode go to the [edit interfaces coc1-fpc/pic/port].
  4. Partition the channelized OC1 interface into T1 interfaces by including the partition and interface-type statements and specify t1 interface type.
  5. If your network equipment uses M13 or C-bit parity, convert the channelized OC1 interface into a channelized T3 interface. Go to the [edit interfaces coc1- fpc/pic/port:channel] hierarchy level.
  6. Include the no-partition and interface-type statements and specify ct3 interface type. Note that because the no-partition statement is included, this configuration does not create another level of channelization, as denoted by the number of colons in the resulting interface.
  7. To partition the channelized T3 interface into T1 interfaces go to [edit interfaces ct3-fpc/pic/port:channel] hierarchy level.
  8. Include the partition and interface-type statements and specify t1 interface type.
Note

Class-of-service (CoS) rules cannot be applied to an individual channel configured on channelized IQE interfaces. You can only apply CoS rules to the aggregate bit streams.

Figure 1 shows VT-mapped and M13 or C-bit parity-mapped configurations of T1 interfaces.

Figure 1: T1 Interfaces on a Channelized OC48 PIC
T1 Interfaces
on a Channelized OC48 PIC

Example: Configuring T1 Interfaces

Configure the following T1 interfaces:

VT-Mapped Configuration

M13 or C-bit Parity-Mapped Configuration

Configuring Fractional T1 Interfaces

By default, all the time slots on a channelized T1 interface are used. To configure a fractional T1 interface on a Channelized OC48 IQE PIC, perform the following tasks:

  1. Configure a T1 interface. For more information, see Configuring T1 Interfaces.
  2. In the configuration mode go to the [edit interfaces t1-fpc/pic/port<:channel> t1-options] hierarchy level.
  3. Configure the number of time slots allocated to the T1 interface by including the timeslots statement.

For channelized T1 interfaces, the time-slot range is from 1 through 24. You can designate any combination of time slots. To configure ranges, use hyphens. To configure discontinuous time slots, use commas. Do not include spaces. For more information, see Configuring Fractional T1 Time Slots.

Example: Configuring Fractional T1 Interfaces

Configure a fractional T1 interface that uses time slots 1 through 5 and 10:

Configuring NxDS0 Interfaces

To configure NxDS0 interfaces on a Channelized OC48 IQE PIC, perform the following tasks:

  1. In the configuration mode go to the [edit interfaces coc48-fpc/pic/port:channel] hierarchy level.
  2. Partition the channelized OC48 IQE interface into channelized OC1 interfaces by including the partition, oc-slice, and interface-type statements and specify coc1 interface type.
  3. If your network equipment uses VT mapping, go to the [edit interfaces coc1-fpc/pic/port:channel] hierarchy level.
  4. Partition the channelized OC1 interface into channelized T1 interfaces by including the partition and interface-type statements and specify ct1 interface type.
    Note

    Class-of-service (CoS) rules cannot be applied to an individual channel configured on channelized IQE interfaces. You can only apply CoS rules to the aggregate bit streams.

  5. If your network equipment uses M13 or C-bit parity, convert the channelized OC1 interface into a channelized T3 interface. Go to the [edit interfaces coc1-fpc/pic/port] hierarchy level.
  6. Include the no-partition and interface-type statements and specify ct3 interface type. Note that because the no-partition statement is included, this configuration does not create another level of channelization, as denoted by the number of colons in the resulting interface.
  7. Partition the channelized T3 interface into channelized T1 interfaces at the [edit interfaces ct3-fpc/pic/port:channel] hierarchy level:
  8. Include the partition and interface-type statements and specify ct1 interface type.
  9. Configure channelized NxDS0 interfaces on the channelized T1 interface at [edit interfaces ct1-fpc/pic/port:channel]
  10. Include the partition, timeslots, and interface-type statements ad specify ds interface type

Figure 2 shows VT-mapped and M13 or C-bit parity-mapped configurations of NxDS0 interfaces.

Figure 2: Sample Channelization of OC48 IQE PIC
Sample
Channelization of OC48 IQE PIC

Example: Configuring NxDS0 Interfaces

Configure the following two NxDS0 interfaces with 10 time slots and 4 time slots, respectively:

VT-Mapped Configuration

M13 or C-bit Parity-Mapped Configuration