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Configuring Channelized IQ and IQE SONET/SDH Loop Timing

 

The loop-timing and no-loop-timing statements apply only to E1 and T1 interfaces you configure on channelized IQ and IQE PICs. If you attempt to include these statements on any other interface type, they are ignored.

To configure SONET/SDH or DS3-level clocking:

  1. In configuration mode, go to the [edit interfaces interface-name sonet-options] hierarchy level or to the [edit interfaces ct3-fpc/pic/port t3-options] hierarchy level.
  2. Configure SONET/SDH or DS3-level clocking. By default, internal clocking (line timing) is used on channelized IQ and IQE interfaces.

To configure the default line timing explicitly:

  1. In configuration mode, go to the [edit interfaces interface-name sonet-options] hierarchy level or to the [edit interfaces ct3-fpc/pic/port t3-options].
  2. Configure the default line timing explicitly.

To configure clocking for all channelized IQ and IQE PICs which is supported on all channels.

  1. In configuration mode, go to the [edit interfaces type-fpc/pic/port] hierarchy level.
  2. Configure the clocking option. If you do not include the clocking statement, the individual interfaces use internal clocking by default.

For more information, see Configuring the Clock Source and Clock Sources on Channelized Interfaces.