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Configuring PHY Timestamping

 

The PHY timestamping refers to the timestamping of the IEEE 1588 event packets at the 1-Gigabit Ethernet and 10-Gigabit Ethernet PHY. Timestamping the packet in the PHY results in higher stability of recovered clock. The PHY timestamping on ACX updates the correction field of the packet. ACX supports PHY timestamping in ordinary clock and boundary clock modes.

Note

PHY timestamping is supported only on ACX500 line of routers.

The following points need to be considered while configuring PHY timestamping in ACX routers:

  • PHY timestamping is enabled or disabled on all the PHYs. You cannot selectively enable or disable PHY timestamping on a particular interface.

  • When PHY timestamping is enabled, the transparent clock functionality is also enabled.

Note

The PHYs on ACX do not support transparent clock functionality for PTP-over-MPLS. You should not enable transparent clock or PHY timestamping if PTP is transported over MPLS.

In ACX2000 router, the transparent clock operation is not supported on the 10-Gigabit Ethernet port.

To enable PHY timestamping on ACX routers, configure clock-mode (ordinary clock or boundary clock) along with the transparent-clock CLI statement at the [edit protocols ptp] hierarchy.

Note

Starting in Junos OS Release 17.1 onwards, to configure transparent clock, include the e2e-transparent CLI command at the [edit protocols ptp] hierarchy level. Prior to Junos OS Release 17.1, to configure transparent clock, include the transparent-clock CLI command at the [edit protocols ptp] hierarchy level.

Enabling PHY Timestamping for Ordinary Clock Slave

The following procedure enables you to configure PHY timestamping for ordinary clock slave in ACX:

  1. Configure the clock mode as ordinary.
  2. Configure the transparent clock.
  3. Configure the interface for slave clock. For information on configuring PTP slave clock interface, see Configuring a PTP Slave Clock.

Enabling PHY Timestamping for Boundary Clock

The following procedure enables you to configure PHY timestamping for boundary clock in ACX:

Note

PHY timestamping is supported only on ACX500 line of routers.

  1. Configure the clock mode as boundary.
  2. Configure the transparent clock.
  3. Configure the interface for slave clock. For information on configuring PTP slave clock interface, see Configuring a PTP Slave Clock.
  4. Configure the interface for master clock. For information on configuring PTP master boundary clock, see Configuring a PTP Master Boundary Clock.

Enabling PHY Timestamping for Grandmaster Clock

The following procedure enables you to configure PHY timestamping for grandmaster clock in ACX:

Note

In ACX Series routers, the grandmaster functionality is supported only on ACX500 router.

  1. Configure the clock mode as ordinary.
  2. Configure the transparent clock.
  3. Configure the interface for master clock. For information on configuring PTP master boundary clock, see Configuring a PTP Master Boundary Clock.