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Configuring T1 and NxDS0 Interfaces

 

To configure T1 interfaces on a Channelized OC3 IQ or IQE PIC, perform the following tasks:

  1. Partition the channelized OC3 interface into channelized OC1 interfaces by including the partition, oc-slice, and interface-type statements at the [edit interfaces coc3-fpc/pic/port] hierarchy level, specifying the coc1 interface type:

  2. If your network equipment uses VT mapping, partition the channelized OC1 interface into T1 interfaces by including the partition and interface-type statements at the [edit interfaces coc1-fpc/pic/port:channel] hierarchy level, specifying the t1 interface type:

  3. If your network equipment uses M13 or C-bit parity, convert the channelized OC1 interface into a channelized T3 interface by including the no-partition and interface-type statements at the [edit interfaces coc1-fpc/pic/port:channel] hierarchy level, specifying the ct3 interface type:

    Note

    Class-of-service (CoS) rules cannot be applied to an individual channel configured on channelized IQ interfaces. You can only apply CoS rules to the aggregate bit streams.

    Note that because the no-partition statement is included, this configuration does not create another level of channelization, as denoted by the number of colons in the resulting interface.

  4. To configure T1 interfaces, partition the channelized T3 interface into T1 interfaces by including the partition and interface-type statements at the [edit interfaces ct3-fpc/pic/port:channel] hierarchy level, specifying the t1 interface type:

  5. To configure NxDS0 interfaces, partition the channelized T3 interface into channelized T1 interfaces by including the partition and interface-type statements at the [edit interfaces ct3-fpc/pic/port:channel] hierarchy level and specifying the ct1 interface type:

    Note

    Class-of-service (CoS) rules cannot be applied to an individual channel configured on channelized IQ interfaces. You can only apply CoS rules to the aggregate bit streams.

    Figure 1 shows VT-mapped and M13 or C-bit parity-mapped configurations of T1 IQ interfaces.

    Figure 1: T1 Interfaces on a Channelized OC3 PIC
    T1 Interfaces on a Channelized OC3
PIC
  6. Configure channelized NxDS0 IQ interfaces on the channelized T1 IQ interface by including the partition, timeslots, and interface-type statements at the [edit interfaces ct1-fpc/pic/port:channel] hierarchy level, specifying the ds interface type:

Figure 2 shows VT-mapped and M13 or C-bit parity-mapped configurations of NxDS0 IQ interfaces.

Figure 2: Sample Channelization of OC3 IQ or IQE PIC
Sample Channelization of OC3 IQ or
IQE PIC

Example: Configuring T1 and NxDS0 Interfaces

Configure the following T1 interfaces:

VT-Mapped Configuration

M13 or C-bit Parity-Mapped Configuration

Configure the following two NxDS0 interfaces with 10 time slots and 4 time slots, respectively:

VT-Mapped Configuration

M13 or C-bit Parity-Mapped Configuration

Example: Setting Remote Loopback and Running BERT Tests on NxDS0 Interfaces

For Channelized OC3 IQ and IQE PICs, if you need remote loopback on a far-end NxDS0 interface, and you are running a BERT test from the local NxDS0 interface, you must set remote loopback on the far-end router’s associated channelized T1 interface (ct1). To do this, include the loopback remote statement at the [edit interfaces ct1-fpc/picport t1-options] hierarchy level. For example:

Local router:

Remote router: