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Configuring the Junos OS to Enable Larger Delay Buffers for T1, E1, and DS0 Interfaces Configured on Channelized IQ PICs

 

By default, T1, E1, and NxDS0 interfaces configured on channelized IQ PICs are limited to 100,000 microseconds of delay buffer. (The default average packet size on the IQ PIC is 40 bytes.) For these interfaces, it might be necessary to configure a larger buffer size to prevent congestion and packet dropping.

To ensure traffic is queued and transmitted properly, you can configure a buffer size larger than the default maximum. To set the average packet size used to calculate the number of notification queue entries in the IQ PIC to 256 bytes, include the q-pic-large-buffer large-scale statement at the [edit chassis fpc slot-number pic pic-number] hierarchy level:

On a TX Matrix router or a TX Matrix Plus router, include the q-pic-large-buffer large-scale statement at the [edit chassis lcc number fpc slot-number pic pic-number] hierarchy level:

Note

When you commit the configuration after including the q-pic-large-buffer statement for a PIC, the Junos OS temporarily takes the PIC offline and brings it back online before the new configuration is activated and becomes the current operational configuration.

This statement sets the maximum buffer size. (See Maximum Delay Buffer with q-pic-large-buffer Statement Enabled.)