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Example: Configuring Channelized T3 IQ Interfaces

 

Configure a channelized T3 interface as an unpartitioned, clear channel.

Configuring a T3 Interface

Configuring NxDS0 and T1 Interfaces

Figure 1 shows the following interfaces on a Channelized DS3 IQ or IQE PIC:

  • A channelized T1, which is partitioned into NxDS0 interfaces

  • T1 interfaces

Figure 1: Sample Channelization of DS3 IQ or IQE PIC
Sample Channelization of DS3 IQ or
IQE PIC