Example: Configuring Channelized T3 IQ Interfaces
Configure a channelized T3 interface as an unpartitioned, clear channel.
Configuring a T3 Interface
Configuring NxDS0 and T1 Interfaces
Figure 1 shows the following interfaces on a Channelized DS3 IQ or IQE PIC:
A channelized T1, which is partitioned into NxDS0 interfaces