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Clock Sources for PTX Series Packet Transport Routers

 

System clocking on PTX Series Packet Transport Routers is controlled by a Centralized Clock Generator (CCG). The CCG is capable of deriving a master clock from a valid source and synchronizing all interfaces on the chassis to this master clock. The CCG plugs into the rear of the chassis. A pair of CCGs installed in the chassis provide a redundant fallback option.

Synchronous Ethernet is configured on external primary and secondary interfaces that use building-integrated timing system (BITS), SDH Equipment Timing Source (SETS) timing sources, or an equivalent quality timing source such as GPS. On the PICs, the transmit clock of the interface is synchronized to a BITS or SETS timing source and is traceable to the timing source within the network.

PTX Series Packet Transport Routers can use an internal clock source or it can extract clocking from an external source.

Clock sources and specifications include:

  • The PTX Series Packet Transport Router clock is a Stratum 3E-compliant clock with Free Run +/- 4.6 ppm/20 years, Holdover +/- 0.01 ppm/24 hours, and Drift +/- 0.001 ppm/24 hours.

  • The internal clock is based on Freerun OCXO with +/- 10 ppb accuracy.

  • External clocking includes a choice of GPS-based clock recovery (5 MHz and 10 MHz) or BITS-T1/E1 Line synchronization (1.544 MHz and 2.048 MHz).

  • Synchronous Ethernet is supported based on the ITU-T G.8261, ITU-T G.8262, and ITU-T G8264 specifications with line timing from the 10-Gigabit Ethernet, 40-Gigabit Ethernet, or 100-Gigabit Ethernet interface.

    Synchronous Ethernet is a key requirement for circuit (emulation) services and mobile radio access technologies. Synchronous Ethernet supports sourcing and transfer of frequency for synchronization purposes for both wireless and wireline services and is primarily used for mobile backhaul and converged transport.

Figure 1: Clocking Example for PTX Series Packet Transport Routers
Clocking Example for PTX Series Packet Transport Routers

In this example, the interface et-7/1/1 is configured as the primary clock source and GPS1 as the secondary clock source.

Note that you can specify the primary and secondary clock sources provided that the clock source meets the necessary qualification as set by the clock algorithm. However, in the absence of any user-selected clock source, the clock source with the best quality level is selected by the clock algorithm in the router. Note that the user selection is honored even when better quality level clock sources are available. You can select the clock source with the request chassis synchronization switch clock-source operational mode command. For more information, see request chassis synchronization switch.

Note

The clock sources used as primary or secondary clock sources cannot originate from the same FPC.

For more information about clock source ports, see PTX3000 Clocking Port Cable Specifications and Pinouts, PTX5000 Centralized Clock Generator Description, and Connecting the PTX5000 to an External Clocking Device.