Scheduler Delay Buffering on MIC and MPC Interfaces
To control congestion at the output stage, you can configure the delay-buffer bandwidth. Scheduler delay-buffer bandwidth provides packet buffer space to absorb burst traffic up to the specified duration of delay. After the specified delay buffer becomes full, packets with 100 percent drop probability are dropped from the head of the buffer.
MIC and MPC interfaces support the following default scheduler delay buffer sizes:
For delay buffer rates below 1 Gbps, the interfaces support delay buffer capacity for 500 ms of buffering.
For delay buffer rates of 1 Gbps and faster, the interfaces support delay buffer capacity for 100 ms of buffering.
All tunnel interfaces configured on MIC and MPC interfaces support delay buffer capacity for 100 ms of buffering.
You can configure an explicit buffer size ranging from 4 KB to 256 MB, depending on the MIC or MPC model. However, MIC and MPC interfaces do not support the large delay buffer size configuration statement q-pic-large-buffer
Interfaces hosted on MIC and MPC line cards have a certain granularity in the application of configured delay buffer parameters. In other words, the observed hardware value might not exactly match the user-configured value. Nevertheless, the derived values are as close to the configured values as allowed.
When you configure an explicit buffer size, there are 256 points available and the closest point is chosen. High-priority and medium-priority queues use 64 points, and the low-priority queues uses 128.