Understanding ATM QoS or Shaping
M7i, M10i, M40e, M120, and M320 routers with 4-port Channelized OC3/STM1 Circuit Emulation PICs and 12-port T1/E1 Circuit Emulation PICs and MX Series routers with Channelized OC3/STM1 (Multi-Rate) Circuit Emulation MIC with SFP and 16-port Channelized E1/T1 Circuit Emulation MIC support ATM pseudowire service with QoS features for ingress and egress direction traffic shaping. Policing is performed by monitoring the configured parameters on the incoming traffic and is also referred to as ingress shaping. Egress shaping uses queuing and scheduling to shape the outgoing traffic. Classification is provided per virtual circuit (VC). To configure ATM QoS or shaping, see Configuring ATM QoS or Shaping.
The following QoS features are supported:
CBR, rtVBR, nrtVBR, and UBR
Policing on a per VC basis
Independent PCR and SCR policing
Counting policing actions
Circuit Emulation PICs provide pseudowire service towards the core. This section describes the ATM service QoS features.
Circuit Emulation PICs support two types of ATM pseudowires:
Only ATM pseudowires are supported; no other encapsulation types are supported.
Since cells within a VC cannot be re-ordered, and since only the VC is mapped to a pseudowire, classification is not meaningful in the context of a pseudowire. However, different VCs can be mapped to different classes of traffic and can be classified in the core network.
Such a service would connect two ATM networks with an IP/MPLS core. Figure 1 shows that the routers marked PE are equipped with Circuit Emulation PICs.
Figure 1 shows that traffic is shaped in the egress direction towards the ATM networks. In the ingress direction towards the core, the traffic is policed and the appropriate action is taken. Depending on a very elaborate state machine in the PIC, the traffic is either discarded or sent towards the core with a particular QoS class.
Each port has four transmit queues and one receive queue. Packets arrive from the ingress network on this single queue. Remember that this is per port and multiple VCs arrive on this queue, each with its own QoS class. To simplify unidirectional connections, only a Circuit Emulation PIC (PE 1 router) to Circuit Emulation PIC (PE 2 router) configuration is shown in Figure 2.
Figure 2 shows the four VCs with different classes mapped to different pseudowires in the core. Each VC has a different QoS class and is assigned a unique queue number. This queue number is copied to the EXP bits in the MPLS header as follows:
Qn concatenated with CLP -> EXP
Qn is 2 bits and can have four combinations; 00, 01, 10, and 11. Since CLP cannot be extracted from the PIC and put into each packet prefix, it is 0. The valid combinations are shown in Table 1.
Table 1: Valid EXP Bit Combinations
For example, VC 7.100 has CBR, VC 7.101 has rt-VBR, 7.102 has nrt-VBR, 7.103 has UBR, and each VC is assigned a queue number as follows:
VC 7.100 -> 00
VC 7.101 -> 01
VC 7.102 -> 10
VC 7.103 -> 11
Lower queue numbers have higher priorities.
Each VC will have the following EXP bits:
VC 7.100 -> 000
VC 7.101 -> 010
VC 7.102 -> 100
VC 7.103 -> 110
A packet arriving on VC 7.100 at the ingress router has the queue number 00 before being forwarded to the Packet Forwarding Engine. The Packet Forwarding Engine then translates this to 000 EXP bits in the core. At the egress router, the Packet Forwarding Engine retranslates this to queue 00 and stamps the packet with this queue number. The PIC receiving this queue number sends the packet out on the transmit queue that is mapped to queue 0, which could be the highest priority transmit queue on the egress side.
To briefly summarize, shaping and policing are possible. Classification is possible at the VC level by mapping a specific VC to a particular class.