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Known Issues

 

This section lists the known issues in hardware and software in Junos OS Release 16.2R2 for the PTX Series.

For the most complete and latest information about known Junos OS defects, use the Juniper Networks online Junos Problem Report Search application.

General Routing

  • PTX 100GbE-LR4 interfaces may flap when the reference clock switches over from "line clock" to "holdover" initiated by offlining the PIC, on which the "line clock" sources reside. When PTX 100GbE-LR4 interface uses the "line clock" sources and when it does not have any external clocks from BITS-a or BITS-b, offlining the PIC, which is recovering clock from line, brings the "line clock" down and the reference clock is switched from "line clock" to "holdover". This reference clock transition may cause a large clock phase-shift in the 100GbE-LR4 CFP modules, and this phase-shift may cause the output optical pulse waveform distortion on the 100GbE-LR4 interfaces. Hence, it results in interface flap. This issue cannot be fixed by software due to hardware limitation. PR1130403

  • While upgrading from 15.1F based images to 16.x+ images or downgrading from 16.x+ images to 15.1F based images, if validate option is enabled, there may be a chassisd crash and upgrade/downgrade will fail. This issue should not be seen if both base and target images are from 15.1F train or 16.x+ train. PR1171652

  • Major errors might be seen on MPC3/FPC3 with 1X100 and 5x100 DWDM MIC/PIC. user@router> show chassis alarms no-forwarding 1 alarms currently active Alarm time Class Description <timestamp> . Major FPC 3 Major Errors The following messages are seen in the logs: fpc3 Cmerror Op Sub Set: CORDOBA : CORDOBA(3/0) link 0 : DSP loss of lock fpc3 Cmerror Op Sub Set: CORDOBA : CORDOBA(3/0) link 0 : DFE tuning failed alarmd[16241]: Alarm set: FPC color=RED, class=CHASSIS, reason=FPC 3 Major Errors craftd[15906]: Major alarm set, FPC 3 Major Errors. PR1212089

MPLS

  • LDP to BGP stitching with eBGP indirect nexthop having implicit null label had never worked on PTX Series routers. It works only when BGP indirect nexthop has real label. Workaround (1) Ensure the peer advertises real label by adding another router between the egress and Ingress PE. (2) Use IBGP that gets resolved over LDP or RSVP-TE LSPs. This will ensure that the BGP indirect nexthop has real label. PR1254702

Platform and Infrastructure

  • On PTX Series router, parity memory errors might happen in pre-classifier engines within a MPC. Packets will be silently discarded, as such errors are not reported and makes it harder to diagnose. After the change in this PR, CM-ERRORs, such as syslogs and alarms, will be raised when parity memory errors occur. PR1059137