Using Send Timing (ST) Clocking for Higher Speed Circuits with Transparent Encoding

Figure 1 shows the issue of delay and jitter where a transparent encoded circuit connects a DCE to a DTE. The circuit is set up as follows:

• The high-speed clock and data lines (shown in red) are aligned by a FIFO buffer at the DCE.

• The signaling leads (shown in blue) are passed end-to-end without going through the FIFO buffer. The signaling paths that carry non-timing-critical signals are subject to delay and jitter.

The problem is that when a FIFO buffer is used at one end of the circuit, an additional clock path from the DCE to the DTE is needed to carry a clock to the DTE so that it can return a DTE-to-DCE clock that is in phase with the data. This DTE-to-DCE clock is needed to clock the FIFO input. Normally, one of the signal lead paths carries this transmit clock. However, when the circuit is running at speeds above 32k, the delay and jitter on these paths make these signal choices nonoptimal.

Figure 1: High-Speed and Low-Speed Paths with Transparent Encoding

To solve the issue of delay and jitter associated with the signaling leads, you can use the ST interface signal to feed or sink the RTS-to-CTS signal path. By using the ST interface signal instead of the RTS-to-CTS signal path, delay and jitter are removed from that signal path. Figure 2 shows a transparent-encoded circuit with the additional ST functionality:

• At the DCE, the RTS-to-CTS signal path is configured to use ST (as an input from the DCE) to feed that signal path through the network.

• At the DTE, that signal is placed onto the ST lead, which is configured as an output.

Figure 2: Transparent Encoding Using ST Clocking

When you configure transparent encoding to use the ST lead instead of RTS/CTS, you can specify whether or not ST is an input lead.