Using Phase-Correction FIFO Buffer with Transparent Encoding
The transparent encoding feature provides a phase-correction FIFO buffer. This FIFO buffer aligns the clock and data phase relationship on a transparent encoded circuit in which the clock travels in one direction through the network, and the data travels in the opposite direction. The transparent FIFO buffer is needed because of the latency of signal transport over the IP network.
Figure 1 shows the phase-correction FIFO buffers. You can enable the phase-correction FIFO buffer at either end of the circuit. You would not enable the FIFO buffer at both ends of the circuit.
Figure 2 shows the paths of the clock and data through the phase-correction FIFO buffer that is enabled on the transparent circuit on the right.
The clock enters the network from the DCE, goes to the DTE, and then clocks data into the network on the DTE. The clock is also looped back on the DTE to enter the network in phase with the data as it travels from the DTE to the DCE.
The data enters the FIFO buffer in phase with the clock passing through the network from the DTE to the DCE, while data is clocked out of the FIFO buffer with the clock that entered the network from the DCE, which is in phase with the user clock.
Like in TRANS encoding, you can use the 16 bit phase correction FIFO in TRANS 8 encoding to accommodate the problems that can be caused by the high latency in the circuit whether or not the remote DCE device can accept TT input or not.
When the customer DCE device can support the TT signal returned by the DTE, the phase correction FIFO is not needed. The DCE transmit clock (ST) is sampled and carried downstream to the DTE, where it is used to generate the upstream data that is sent back to the customer DCE. This clock data is also sent as the DTE transmit clock (TT) to travel along with the data in phase. When these signals get back to the customer DCE device, they are still in phase (same delay through the network), so the customer DCE can use the TT signal to recover the transmit data on the SD lead.
Consider a scenario in which the customer's upstream DCE does not use the TT signal for capturing upstream data, and instead uses the ST clock. Here, due to the latency of the ST clock traveling downstream and the time taken for the return trip of the data, it is difficult to ensure error-free data transport. In such a scenario, you can use phase correction FIFO to ensure error-free data transport.
The SD or TT clock and data signals get back to the upstream CTP device, where the data is clocked into the FIFO using the TT clock, which is in phase. This data is clocked out of the FIFO using the upstream ST clock, and the data is realigned to be in phase with the ST clock.