Channelized Interfaces Overview

Channelized interfaces enable you to configure a number of individual channels that subdivide the bandwidth of a larger interface and minimize the number of Physical Interface Cards (PICs) that an installation requires.

NOTE: Channelized intelligent queuing (IQ) interfaces require M-series Enhanced Flexible PIC Concentrators (FPCs). Wherever JUNOS configuration guides refer to channelized interfaces and PICs without the "intelligent queuing" or "IQ" descriptor, they are referring to the original channelized interfaces and PICs. For SONET/SDH interfaces you configure on Channelized OC3 IQ, Channelized OC12 IQ, and Channelized STM1 IQ PICs, aggregated SONET is not supported. For channelized IQ logical interfaces, you can configure class of service (CoS). For more information, see the JUNOS Class of Service Configuration Guide.

This chapter provides a high-level overview of channelized interfaces, focusing mainly on the capabilities, properties, and structure of channelized IQ interfaces:

• Channelized Interface Capabilities
• Data-Link Connection Identifiers on Channelized Interfaces
• Clock Sources on Channelized Interfaces
• Channelized E1 and T1 PIM Properties
• Channelized IQ Interface Properties
• Structure of Channelized IQ PICs