Configuring Channelized OC3 IQ Interfaces

Channelized intelligent queuing (IQ) interfaces allow arbitrary and dynamic channelization of serial links, allowing greater flexibility than regular channelized interfaces.

On a Channelized OC3 IQ PIC, you can configure the following interface types:

• One OC3 SONET/SDH interface
• Up to three T3 interfaces
• Up to 84 T1 interfaces
• Up to 336 NxDS0 interfaces on an M-series platform
• Up to 768 NxDS0 interfaces on a T-series platform

Figure 19 shows an example of how a Channelized OC3 PIC might be partitioned. In the figure, the OC3 SONET interface would be a standalone interface because it would use the entire bandwidth of the PIC.

Figure 19: Channelized OC3 IQ Interface Example for Show Interfaces Controller

You can configure the following encapsulation types:

• PPP
• Frame Relay
• Cisco HDLC
• CCC
• TCC

For more information about interface encapsulation, see Configuring Interface Encapsulation and "Configuring Interface Encapsulation".

To configure channelized interfaces, include the following statements at the [edit interfaces interface-name] hierarchy level:

[edit interfaces interface-name]

no-partition interface-type type;

partition partition-number oc-slice oc-slice-range interface-type type;

partition partition-number timeslots time-slot-range interface-type type;

This chapter describes how to configure interfaces on a Channelized OC3 IQ PIC, discussing the following topics:

• Partitions, OC Slices, Interface Types, and Time Slots
• Configuring a Clear Channel
• Configuring T3 IQ Interfaces
• Configuring T1 and NxDS0 Interfaces
• Configuring Fractional T1 IQ Interfaces
• Configuring Link PIC Failover