Channelized Intelligent Queuing Interfaces

Juniper Networks M-series and T-series routing platforms support enhanced channelized interfaces called channelized intelligent queuing (IQ) interfaces. Formerly known as Channelized Q Performance Processor (QPP) interfaces, the interfaces provide a more flexible way to configure channels than earlier channelized Physical Interface Cards (PICs) and offer a simplified configuration structure self-contained in the [edit interfaces] hierarchy level. Channelized IQ interfaces also enable class of service at the PIC level rather than the Flexible PIC Concentrator (FPC) level.

This guide highlights the features of channelized PICs with intelligent queuing and their similarities to and differences from the original channelized interfaces.

This feature guide covers these topics:

• Overview
• System Requirements
• Terms and Acronyms
• Configuring Channelized IQ Interfaces

• Example: Clear Channel Configuration for a Channelized OC12 IQ Interface
• Checking Your Work
• Example: Complex Configuration for a Channelized OC12 IQ Interface
• Checking Your Work
• Example: Converting a Channelized OC12 IQ PIC to a Channelized STM4 IQ Interface
• Checking Your Work
• Example: Channelized OC3 IQ Interface Configuration
• Checking Your Work
• Example: Channelized DS3 IQ Interface Configuration
• Checking Your Work
• Example: Channelized T1 IQ Interface Configuration
• Checking Your Work
• Example: Channelized STM1 IQ Interface Configuration
• Checking Your Work
• Example: Channelized E1 IQ Interface Configuration
• Checking Your Work

• Configuring Class of Service for Channelized IQ Interfaces

• Example: DLCI Class of Service on a Channelized IQ Interface Configuration
• Checking Your Work

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• Revision History