Example: Channelized STM1 IQ Interface Configuration
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This example shows how to configure a channelized STM1 IQ interface on M-series or T-series routing platforms. Figure 8 shows the breakdown of one channelized STM1 IQ interface into a variety of channels and the conversion of the second interface into a clear channel STM1.
For the first interface, you must first convert the STM1 interface into a channelized Administrative Unit 4 (AU-4) interface with the
no-partitionandinterface-type cau-4statements at the[edit interfaces cstm1-fpc/pic/port]hierarchy level. You must specify KLM or ITU-T AU-4 formatting with thevtmappingstatement at the[edit interfaces cau4-fpc/pic/portsonet-options]hierarchy level. From the channelized AU-4 interface, you can create E1 channels or channelized E1 channels. The channelized E1 channels can be further broken into DS0 time slots.To create E1 channels, include the
partitionstatement at the[edit interfaces cau4-fpc/pic/port]hierarchy level with theinterface-type e1option. To create channelized E1 channels, include thepartitionstatement at the[edit interfaces cau4-fpc/pic/port]hierarchy level with theinterface-type ce1option.After you have established a channelized E1 channel, you can split it into a maximum of 31 NxDS0 channels. To create the desired number of NxDS0 channels, include the
partitionstatement with thetimeslotsandinterface-type dsoptions at the[edit interfaces ce1-fpc/pic/port:channel]hierarchy level. Time slot1is reserved in an NxDS0-based channelized E1 channel, so you can use time slots2through32.
To create an NxDS0 channel group, include a range of time slots after thetimeslotsoption.You can also create fractional E1 interfaces on a channelized STM1 IQ interface. To configure a fractional E1 interface, include the
partitionstatement at the[edit interfaces cau4-fpc/pic/port]hierarchy level and select theinterface-type e1option. After you commit this part of the configuration, a clear channel E1 interface is established. You can configure standard E1 options on this interface. To fractionalize the E1 interface, include thetimeslotsstatement at the[edit interfaces e1-fpc/pic/porte1-options]hierarchy level. Time slot1is reserved in a fractional E1 channel, so you can use time slots2through32.In the second interface shown in Figure 8, you convert the channelized STM1 IQ interface into a clear channel STM1 interface. To configure, include the
no-partitionandinterface-type sostatements at the[edit interfaces cstm1-fpc/pic/port]hierarchy level.[edit]interfaces {cau4-0/0/0 {partition 1-10 interface-type e1;# Creates interfaces e1-0/0/0:1 through :10.partition 11 interface-type ce1;# Creates a single channelized E1 interface:sonet-options { # e1-0/0/0:11.vtmapping itu-t;# This selects ITU-T as the VT mapping frame format.}}cstm1-0/0/0 {no-partition interface-type cau4;# Creates a channelized AU-4 interface:} # cau4-0/0/0.e1-0/0/0:1 {# Channel e1-0/0/0:1 is a fractional E1 interface.encapsulation ppp;e1-options {timeslots 2-21;# Setting time slots on an E1 channel makes a fractional E1.}unit 0 {family inet {address 10.133.0.1/30;}}}e1-0/0/0:2 {# Channels e1-0/0/0:2 through :10 are standard E1 interfaces.encapsulation ppp;unit 0 {family inet {address 10.133.0.5/30;}}}...e1-0/0/0:10 {encapsulation ppp;unit 0 {family inet {address 10.133.0.37/30;}}}ce1-0/0/0:11 {# Channel ce1-0/0/0:11 is a channelized E1 interface.partition 1 timeslots 2-11 interface-type ds;# These statements createpartition 2 timeslots 12-21 interface-type ds;# channel groups.partition 3 timeslots 22-31 interface-type ds;partition 4 timeslots 32 interface-type ds;# This statement creates a} # single NxDS0 channel.ds-0/0/0:11:1 {# This channel group contains 10 DS0s.unit 0 {family inet {address 10.134.1.1/30;}}}ds-0/0/0:11:2 {# This channel group contains 10 DS0s.unit 0 {family inet {address 10.134.2.1/30;}}}ds-0/0/0:11:3 {# This channel group contains 10 DS0s.unit 0 {family inet {address 10.134.3.1/30;}}}ds-0/0/0:11:4 {# Channel ds-0/0/0:11:4 is a standard DS0 interface.unit 0 {family inet {address 10.134.4.1/30;}}}}Figure 9 shows a visual representation of the E1-to-STM1 SDH mapping method used by Juniper Networks in its channelized STM1 IQ interface.
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