Configuring the Scheduler Buffer Size
To control congestion at the output stage, you can configure the delay-buffer bandwidth. The delay-buffer bandwidth provides packet buffer space to absorb burst traffic up to the specified duration of delay. Once the specified delay buffer becomes full, packets with 100 percent drop probability are dropped from the head of the buffer.
By default, the buffer sizes for queues 0 through 7 are 95, 0, 0, 5, 0, 0, 0, and 0 percent of the total available buffer space.
To configure the buffer size, include the
buffer-sizestatement at the[edit class-of-serviceschedulersscheduler-name] hierarchy level:[edit class-of-service schedulersscheduler-name]buffer-size (percentpercentage| remainder | temporalmicroseconds);For each scheduler, you can configure the buffer size as one of the following:
- A percentage of the total buffer
- The remaining buffer available. The remainder is the buffer percentage that is not assigned to other queues. For example, if you assign 40 percent of the delay buffer to queue 0, allow queue 3 to keep the default allotment of 5 percent, and assign the remainder to queue 7, then queue 7 uses approximately 55 percent of the delay buffer.
- A temporal value, in microseconds. For the temporal setting, the queuing algorithm starts dropping packets when it queues more than a computed number of bytes. This maximum is computed by multiplying the logical interface speed by the configured temporal value. The buffer size temporal value differs by platform type, as shown in Table 14.
For information about configuring large buffer sizes on IQ PICs, see Configuring Large Delay Buffers for Slower Interfaces.
Configuring Large Delay Buffers for Slower Interfaces
By default, T1, E1, and NxDS0 interfaces and DLCIs configured on channelized IQ PICs and Gigabit Ethernet VLANs configured on Gigabit Ethernet IQ PICs are limited to 100,000 microseconds of delay buffer. For these interfaces, it might be necessary to configure a larger buffer size to prevent congestion and packet dropping. You can do so on the following PICs:
Congestion and packet dropping occur when large bursts of traffic are received by slower interfaces. This happens when faster interfaces pass traffic to slower interfaces, which is often the case when edge devices receive traffic from the core of the network. For example, a 100,000-microsecond T1 delay buffer can absorb only 20 percent of a 5000-microsecond burst of traffic from an upstream OC3 interface. In this case, 80 percent of the burst traffic is dropped.
Table 14 shows some recommended buffer sizes needed to absorb typical burst sizes from various upstream interface types.
To ensure that traffic is queued and transmitted properly on Gigabit Ethernet VLANs, and E1, T1, and NxDS0 interfaces and DLCIs, you can configure a buffer size larger than the default maximum. To enable larger buffer sizes to be configured, include the
q-pic-large-bufferstatement at the[edit chassis fpcslot-numberpicpic-number]hierarchy level:[edit chassis fpcslot-numberpicpic-number]q-pic-large-buffer;When you include the
q-pic-large-bufferstatement in the configuration, the larger buffer is transparently available for allocation to scheduler queues. The larger buffer maximum varies by interface type, as shown in Table 15.
If you configure a delay buffer larger than the new maximum, the candidate configuration can be committed successfully. However, the setting is rejected by the packet forwarding component, the default setting is used instead, and a system log warning message is generated.
For interfaces that support DLCI queuing, the large buffer is supported for DLCIs on which the configured shaping rate is less than or equal to the physical interface bandwidth. For instance, when you configure a Frame Relay DLCI on a Channelized T3 IQ PIC, and you configure the shaping rate to be 1.5 Mbps, the amount of delay buffer that can be allocated to the DLCI is 500,000 microseconds, which is equivalent to a T1 delay buffer. For more information about DLCI queuing, see Associating a Scheduler Map with a DLCI or VLAN.
The larger buffer sizes are enabled for Gigabit Ethernet IQ VLANs but not for physical Gigabit Ethernet interfaces. Therefore, the limitations for physical Gigabit Ethernet IQ interfaces remain as shown in Table 13 (50,000 microseconds on T-series and M320 platforms and 200,000 microseconds on other M-series platforms).
For NxDS0 interfaces, the larger buffer sizes can be up to 4,000,000 microseconds, depending on the number of DS0 channels in the NxDS0 interface. For slower NxDS0 interfaces with fewer channels, the delay buffer can be relatively larger than for faster NxDS0 interfaces with more channels. This is shown in Table 15. To calculate specific buffer sizes for various NxDS0 interfaces, see Maximum Delay Buffer for NxDS0 Interfaces.
You can allocate the delay buffer as either a percentage or a temporal value. The resulting delay buffer is calculated differently depending how you configure the delay buffer, as shown in Table 16.
Table 16: Delay Buffer Calculations
Maximum Delay Buffer for NxDS0 Interfaces
Because NxDS0 interfaces carry less bandwidth than a T1 or E1 interface, the buffer size on an NxDS0 interface can be relatively larger, depending on the number of DS0 channels combined. The maximum delay buffer size is calculated with the following formula:
Interface Speed * Maximum Delay Buffer Time = Delay Buffer SizeFor example, a 1xDS0 interface has a speed of 64 kilobits (Kb) per second. At this rate, the maximum delay buffer time is 4,000,000 microseconds. Therefore, the delay buffer size is 32 KB:
64 Kb per second * 4,000,000 microseconds = 32 kilobytes (KB)Table 17 shows the delay buffer calculations for NxDS0 interfaces from 1xDS0 through 32xDS0.
Example: Configuring Large Delay Buffers for Slower Interfaces
Set large delay buffers on interfaces configured on a Channelized DS3 IQ PIC. The CoS configuration binds a scheduler map to the interface specified in the chassis configuration. For information about the delay buffer calculations in this example, see Table 16.
chassis {fpc 3 {pic 0 {q-pic-large-buffer; # ChDS3-IQ in FPC slot 3, PIC slot 0}}}class-of-service {interfaces {t1-3/0/0:1 {scheduler-map large-buf-sched-map;}}scheduler-maps {large-buf-sched-map {forwarding-class best-effort scheduler sched-best;forwarding-class expedited-forwarding scheduler sched-expedited;forwarding-class assured-forwarding scheduler sched-assured;forwarding-class network-control scheduler sched-network;}}schedulers {sched-best {transmit-rate percent 20;buffer-size temporal 500000;}sched-expedited {transmit-rate percent 30;buffer-size percent 30;}sched-assured {transmit-rate percent 40;buffer-size percent 40;}sched-network {transmit-rate percent 10;buffer-size percent 10;}sched-extra-buffer {transmit-rate percent 10;buffer-size percent 20;}}}