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Configuring Channelized OC12 Interfaces

Channelized intelligent queuing (IQ) interfaces allow arbitrary and dynamic channelization of serial links, allowing greater flexibility than the channelized interfaces. Figure 19 and Figure 20 illustrate the difference in flexibility between a Channelized OC12 IQ Physical Interface Card (PIC) and a channelized OC12 PIC.


Figure 19: Sample Channelization of OC12 IQ PIC

In Figure 19, a Channelized OC12 IQ PIC is partitioned into the following OC slices:

  1. An OC3 interface
  2. Another OC3 interface
  3. A channelized OC1 partitioned into T1 interfaces
  4. A channelized OC1 converted into a T3 interface
  5. A channelized OC1 partitioned into T1 interfaces and channelized T1s, which are partitioned into NxDS0 interfaces
  6. A channelized OC1 converted into a channelized T3, which is partitioned into T1 interfaces
  7. A channelized OC1 converted into a channelized T3, which is partitioned into T1 interfaces and a channelized T1, which is partitioned into NxDS0 interfaces
  8. A channelized OC1 partitioned into channelized T1s, which are partitioned into NxDS0 interfaces

This is one of thousands of ways to configure a Channelized OC12 IQ PIC. To configure the interfaces shown in Figure 19, see Example: Configuring Channelized OC12 IQ Interfaces.


Figure 20: Sample Channelization of OC12 PIC

Figure 20 shows five T3 channels configured on the Channelized OC12 PIC. You can configure seven additional T3 channels. For more information about configuring Channelized OC12 PICs, see Configuring Channelized OC12 Interfaces.

This chapter is organized as follows:

For examples of channelized OC12 interface configuration, see the following sections:

For a full configuration example, see the JUNOS Feature Guide.

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