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Configure Channelized OC-12 Interfaces

Channelized intelligent queuing (IQ) interfaces allow arbitrary and dynamic channelization of serial links, allowing greater flexibility than the channelized interfaces. Figure 15 and Figure 16 illustrate the difference in flexibility between a Channelized OC-12 IQ PIC and a channelized OC-12 PIC.


Figure 15: Sample Channelization of OC-12 IQ PIC

In Figure 15, a Channelized OC-12 IQ PIC is partitioned into the following OC slices:

  1. An OC-3 interface
  2. Another OC-3 interface
  3. A channelized OC-1 partitioned into T1 interfaces
  4. A channelized OC-1 converted into a T3 interface
  5. A channelized OC-1 partitioned into T1 interfaces and channelized T1s, which are partitioned into NxDS-0 interfaces
  6. A channelized OC-1 converted into a channelized T3, which is partitioned into T1 interfaces
  7. A channelized OC-1 converted into a channelized T3, which is partitioned into into T1 interfaces and a channelized T1, which is partitioned into NxDS-0 interfaces
  8. A channelized OC-1 partitioned into channelized T1s, which are partitioned into NxDS-0 interfaces

This is one of thousands of ways to configure a Channelized OC-12 IQ PIC. To configure the interfaces shown in Figure 15, see Example: Configure Channelized OC-12 IQ Interfaces.


Figure 16: Sample Channelization of OC-12 PIC

Figure 16 shows five T3 channels configured on the Channelized OC-12 PIC. You can configure seven additional T3 channels. For more information about configuring Channelized OC-12 PICs, see Configure Channelized OC-12 Interfaces. To create the interfaces shown in Figure 16, see Configure Aggregated SONET/SDH Interfaces.

This chapter is organized as follows:

For examples of channelized OC-12 interface configuration, see the following sections:

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