Overview

Channelized interfaces allow service providers to customize bandwidth to satisfy the needs of their customers. Whether the subscriber needs DS-0, T1, fractional T1, E1, fractional E1, T3, STM-1, OC-3, or OC-12 service, a channelized PIC can provide the necessary bandwidth today and can be reconfigured to support the customer's expanding network tomorrow. Standard channelized interfaces have been available on Juniper Networks platforms since JUNOS software release 3.4. These original channelized PICs for Juniper Networks M-series routers are available in the following models:

• 1-port Channelized OC-12
• 10-port Channelized E1
• 1-port Channelized STM-1
• 4-port Channelized DS-3
• 1-port and 2-port multichannel Channelized DS-3

These original channelized interfaces provide a single level of channelization and require configuration at both the [edit chassis] and the [edit interfaces] hierarchy levels. Most configuration options must be set on channel 0 and they apply to all channels on these channelized PICs.

The new channelized PICs with intelligent queuing offer several advantages over the original channelized PICs:

• Complete configuration tasks for channelized IQ interfaces are now centralized at the [edit interfaces] hierarchy level.
• Multiple levels of channelization are now possible with channelized IQ interfaces. For example, a channelized OC-12 IQ interface can be divided into channelized OC-1 interfaces, then subdivided into channelized T1 interfaces, and further split into NxDS-0 channels.
• You can now configure interface statements, such as clocking, on individual channels rather than configuring them on channel 0 for all channels at the same hierarchy level.
• Class-of-service processing now occurs on the PIC for channelized IQ interfaces rather than in the FPC.

Channelized PICs with intelligent queuing come in the following model types:

• 1-port Channelized OC-12 IQ PIC
• 4-port Channelized DS-3 IQ PIC
• 10-port Channelized E1 IQ PIC
• 1-port Channelized STM-1 IQ PIC

To determine which type of channelized PIC is installed in your router, use the show chassis hardware command:

user@RouterA> show chassis hardware

Hardware inventory:

Item             Version  Part number  Serial number     Description

Chassis                                20070             M160

Midplane         REV 03   710-001245   AB4123           

FPM CMB          REV 02   710-001642   AB3266           

FPM Display      REV 02   710-001647   AB3038           

CIP              REV 04   710-001593   AB3276           

PEM 0            Rev 03   740-001243   KM28410           DC

PEM 1            Rev 03   740-001243   LF21558           Power Entry Module

PCG 0            REV 03   710-001568   AB3006           

PCG 1            REV 02   710-001568   AB2992           

Routing Engine 0                       20000005dfae3a01  RE-2.0

MCS 0            REV 04   710-001226   AB3208           

MCS 1            REV 04   710-001226   AB3212           

SFM 0 SPP        REV 06   710-001228   AB3103           

SFM 0 SPR        REV 01   710-002189   AB2936            Internet Processor II

SFM 1 SPP        REV 07   710-001228   AG2634           

SFM 1 SPR        REV 03   710-002189   AE3503            Internet Processor II

SFM 2 SPP        REV 06   710-001228   AB2976           

SFM 2 SPR        REV 01   710-002189   AB2938            Internet Processor II

SFM 3 SPP        REV 06   710-001228   AB5826           

SFM 3 SPR        REV 01   710-002189   AB2917            Internet Processor II

FPC 0            REV 03   710-003947   HE0614            E-FPC Type 1

  CPU            REV 01   710-004600   AT3217           

  PIC 0          REV 03   750-005636   BE1826            4x CHDS3 IQ

# This is the Channelized DS-3 IQ PIC.

  PIC 1          REV 07   750-003846   HG5572            1x 800M Crypto

  PIC 2          REV 01   750-004507   BA5341            10x CE1-NxDS0

  PIC 3          REV 06   750-003009   AM6929            4x CT3

#This is the original Channelized T3 PIC.

FPC 1            REV 03   710-003309   AD9434            E-FPC Type 2

  CPU            REV 05   710-001217   AH2707           

  PIC 2          REV 05   750-001900   AD5738            1x OC-48 SONET, SMSR

  PIC 3          REV 04   750-003737   BC1106            4x G/E, 1000 BASE-SX

When you configure channelized IQ interfaces, keep in mind these rules of thumb:

• You normally configure media-related statements and options at the physical interface level (also known as the controller level). This level is indicated by the [edit interfaces cxx-fpc/pic/port] hierarchy level.
• You should always configure HDLC-related statements (for example, bytes, fcs, idle-cycle-flag, mtu, receive-bucket, start-end-flag, and transmit-bucket) and logical interfaces (for example, [edit interfaces interface-name unit unit-number]) on end channels such as DS-0 and T1. Never configure these statements at the controller level.
• Pay attention to the channel numbering rules:

• OC-3 data channels configured on channelized OC-12 IQ interfaces are numbered from 1 to 4.
• T3 channels configured on channelized OC-12 IQ interfaces are numbered from 1 to 12.
• T1 channels configured on either a channelized OC-12 IQ interface or a channelized DS-3 IQ interface are numbered from 1 to 28.
• E1 channels configured on a channelized STM-1 IQ interface are numbered from 1 to 63.
• NxDS-0 timeslots configured on either a channelized OC-12 IQ interface or a channelized DS-3 IQ interface are numbered from 1 to 24.
• NxDS-0 timeslots configured on either a channelized STM-1 IQ interface or channelized E1 IQ interface are numbered from 1 to 31. (Timeslot 0 is reserved.)

• You can configure Automatic Protection Switching (APS) on channelized OC-12 IQ and Multiplex Section Protection (MSP) on channelized STM-1 IQ interfaces. These protection methods are used by SONET/SDH add/drop multiplexers (ADMs) to protect against circuit failures. The JUNOS implementation of APS allows you to protect against circuit failures between an ADM and one or more routers, and between multiple interfaces in the same router. When a device fails, a backup immediately takes over.

You can configure APS at the controller level only. To configure the working and backup circuits, include the working-circuit and protect-circuit statements at the [edit interfaces coc12-fpc/pic/port sonet-options aps] or [edit interfaces cstm1-fpc/pic/port sonet-options aps] hierarchy level.

When you enable the controller-level interface as the working circuit, all partitions under the working circuit are also enabled. This is the default behavior even when APS is not configured. When the backup circuit interface is disabled, all partitions under this protected circuit are also disabled. If the working circuit fails, the interfaces are switched: The working circuit and all its partitions are disabled, and the protect circuit and all its partitions are enabled. You can verify this behavior by entering the show interface controller command. The disabled interfaces are shown as "Admin down" and the enabled interfaces are shown as "Admin up."

• If you use Frame Relay encapsulation on a channelized interface, see Table 2 for the maximum number of data-link connection identifiers (DLCIs) per channel that you can configure at each channel level for various channelized PICs.
  

  NOTE: The actual number of DLCIs you can configure for each channel is determined by the capabilities of your system, such as the number and type of PICs installed. If the number of DLCIs in the configuration exceeds the capabilities of your system, the router might not be able to support the maximum DLCI values shown in Table 2. To determine the capabilities of your system, contact Juniper Networks customer support.

  
  

Table 2: Frame Relay DLCI Limitations for Channelized Interfaces

Original Channelized PICs	Number of DLCIs per level	Range
T3 and T1 level channels	64 for regular mode 3 for sparse mode	0—64 for regular mode 1—1022 for sparse mode (0 is reserved for the Local Management Interface or LMI)
DS-0 level channels	3 for sparse mode	1—1022 for sparse mode (0 is reserved for LMI)
Channelized IQ PICs	Number of DLCIs per level	Range
OC-12 and OC-3 level channels (Channelized OC-12 IQ PIC)	64	1—1022 (0 is reserved for LMI)
T3 level channel (Channelized OC-12 IQ and Channelized DS-3 IQ PICs)	256	1—1022 (0 is reserved for LMI)
STM-1 level channel (Channelized STM-1 IQ PIC)	64	1—1022 (0 is reserved for LMI)
E1 level channels (Channelized STM-1 IQ and Channelized E1 IQ PICs)	64	1—1022 (0 is reserved for LMI)
T1 level channels (Channelized OC-12 IQ and Channelized DS-3 IQ PICs)	64	1—1022 (0 is reserved for LMI)
DS-0 level channels (Channelized DS-3 IQ, Channelized STM-1 IQ, Channelized E1 IQ, and Channelized OC-12 IQ PICs)	16	1—1022 (0 is reserved for LMI)

• You can delete several channelized interfaces simultaneously by using a single command and regular expressions. To delete sequential channelized interfaces, issue the wildcard command with the delete option at the [edit] hierarchy level and specify the configuration hierarchy level and the channelized interfaces to be summarized with a regular expression. For example, to delete channelized interfaces in the range of ds-0/0/0:0:0 through ds-0/0/0:0:23, issue the command wildcard delete interfaces ds-0/0/0:0:*.

In JUNOS Release 6.2 and later, additional Frame Relay encapsulation types on physical interfaces and channels of channelized IQ interfaces are available:

• Extended Frame Relay CCC—Allows you to assign any DLCI number from 1 to 1022 on Frame Relay CCC logical interfaces. To configure, include the extended-frame-relay-ccc statement at the [edit interfaces interface-name encapsulation] hierarchy level.
• Extended Frame Relay TCC—Allows you to assign any DLCI number from 1 to 1022 on Frame Relay TCC logical interfaces. To configure, include the extended-frame-relay-tcc statement at the [edit interfaces interface-name encapsulation] hierarchy level.
• Flexible Frame Relay—Allows you to configure any DLCI number from 1 to 1022 and any combination of Frame Relay encapsulation types on logical interfaces. To configure, include the flexible-frame-relay statement at the [edit interfaces interface-name encapsulation] hierarchy level.

When you configure clocking, bit error rate testing (BERT), C-bit parity, and loopback statements on T3, T1, or DS-0 channels on channelized IQ interfaces, you must follow these guidelines:

• If you include the statements at both the [edit interfaces ct3-fpc/pic/port:channel t3-options] and [edit interfaces t3-fpc/pic/port:channel t3-options] hierarchy levels, channelized T3-level statements are operational and T3-level statements are ignored.
• If you include the statements at both the [edit interfaces ct3-fpc/pic/port:channel t3-options] and [edit interfaces t1-fpc/pic/port:channel t1-options] hierarchy levels, the channelized T3-level statements are operational for the T3 connections and the T1-level statements are operational for the T1 connections.
• Because DS-0 channels do not have a valid clocking option, you must configure clocking for all NxDS-0s at the [edit interfaces ct1-fpc/pic/port:channel t1-options] hierarchy level.
• You configure BERT at the [edit interfaces ct3-fpc/pic/port:channel t3-options] hierarchy level or on any partitioned subchannel of the channelized T3 interface. There are 12 BERT patterns available for DS-0 channels and 28 BERT patterns for T1, channelized T1, T3, and channelized T3 channels within channelized IQ interfaces.
• You can configure loopbacks at the [edit interfaces ct3-fpc/pic/port:channel t3-options] hierarchy level and higher. Local loopbacks recirculate framing information within the local router. Remote loopbacks resend entire frames back to the remote sender. A new loopback called a payload loopback is similar to a remote loopback, but it resends only the data portion of a frame back to the remote sender.
• You can configure C-bit parity at the [edit interfaces ct3-fpc/pic/port:channel t3-options] hierarchy level or on any partitioned subchannel of the channelized T3 interface.

For more details on channelized interface options, see the JUNOS Internet Software Network Interfaces and Class of Service Configuration Guide.