Channelized QPP Interface Properties

On channelized QPP interfaces, you can specify options that are globally applied to all interface types associated with a channelized QPP interface. For example, e1-options statements that you include at the [edit interfaces ce1-fpc/pic/port] hierarchy level apply globally to all T1 and NxDS-0 interfaces that you create by partitioning ce1-fpc/pic/port. Likewise, t3-options statements that you include at the [edit interfaces ct3-fpc/pic/port] hierarchy level apply globally to all T1 and NxDS-0 interfaces that you create by partitioning ct3-fpc/pic/port.

You can also apply interface options at QPP interface level. For example, you can include t1-options statements at the [edit interfaces t1-fpc/pic/port<:channel>] hierarchy level, and ds0-options statements at the [edit interfaces ds-0/1/1<:channel>] hierarchy level.

Only a subset of the interface options is valid on each type of channelized QPP interface. You configure all HDLC information at the QPP interface level, not at the channelized level.

Channelized QPP interfaces do not support Automatic Protection Switching (APS), receive buckets, or transmit buckets.

There are some limitations for channelized QPP interfaces regarding where you place certain statements in the configuration. When you configure clocking, bit error rate testing (BERT), C-bit parity, and loopback statements on T3, T1, or DS-0 channels, you must follow these guidelines:

• If you include the statements at both the [edit interfaces ct3-fpc/pic/port<:channel> t3-options] and [edit interfaces t3-fpc/pic/port<:channel> t3-options] hierarchy levels, the Channelized T3-level statements are valid, and the T3-level statements are ignored.
• If you include the statements at both the [edit interfaces ct3-fpc/pic/port<:channel> t3-options] and [edit interfaces t1-fpc/pic/port<:channel> t1-options] hierarchy levels, the Channelized T3-level statements are operational for the T3 connections and the T1-level statements are operational for the T1 connections.
• Because DS-0 channels do not have clocking capability, you must configure clocking at the [edit interfaces ct1-fpc/pic/port<:channel> t1-options] hierarchy level for Channelized NxDS-0 QPP interfaces.
• You can set BERT at the [edit interfaces t3-fpc/pic/port<:channel> t3-options] hierarchy level or on any partitioned channel of the Channelized T3 interface. There are twelve BERT patterns available for NxDS-0 channels and twenty-eight BERT patterns for T1, Channelized T1, T3 and Channelized T3 interfaces within channelized QPP interfaces.
• For channelized interfaces that use Frame Relay encapsulation, the number of configurable data-link connection identifiers (DLCIs) varies by channelized interface type.