Overview

Channelized interfaces allow service providers to customize bandwidth to satisfy the needs of their customers. Whether the subscriber needs DS-0, T1, fractional T1, E1, fractional E1, T3, OC-3, or OC-12 service, a channelized PIC can provide the necessary bandwidth today and can be reconfigured to support the customer's expanding network tomorrow. Standard channelized interfaces have been available on Juniper Networks platforms since JUNOS software release 3.4. These original channelized PICs for Juniper Networks M-series routers are available in the following models:

• One-port Channelized OC-12
• Ten-port Channelized E1
• One-port Channelized STM-1
• Four-port Channelized DS-3
• One-port and two-port multichannel Channelized DS-3

These original channelized PIC interfaces provide a single level of channelization and require configuration at both the [edit chassis] and the [edit interfaces] hierarchy levels. Most configuration options must be set on channel 0 and they apply to all channels on these channelized PICs.

The new channelized PICs with QPP offer several advantages over the original channelized PICs:

• Complete configuration tasks for channelized QPP interfaces are now centralized at the [edit interfaces] hierarchy level.
• Multiple levels of channelization are now possible with channelized QPP interfaces. For example, a channelized OC-12 QPP interface can be divided into channelized OC-1 interfaces, then subdivided into channelized T1 interfaces, and further split into NxDS-0 channels.
• You can now configure interface statements, such as clocking, on individual channels rather than configuring them on channel 0 for all channels at the same hierarchy level.
• Class-of-service processing now occurs on the PIC for channelized QPP interfaces rather than in the FPC.

Channelized PICs with QPP come in the following model types:

• One-port Channelized OC-12 PIC with QPP
• Four-port Channelized DS-3 PIC with QPP
• Ten-port Channelized E1 PIC with QPP

To determine which type of channelized PIC is installed in your router, use the show chassis hardware command:

user@RouterA> show chassis hardware

Hardware inventory:

Item             Version  Part number  Serial number     Description

Chassis                                20070             M160

Midplane         REV 03   710-001245   AB4123           

FPM CMB          REV 02   710-001642   AB3266           

FPM Display      REV 02   710-001647   AB3038           

CIP              REV 04   710-001593   AB3276           

PEM 0            Rev 03   740-001243   KM28410           DC

PEM 1            Rev 03   740-001243   LF21558           Power Entry Module

PCG 0            REV 03   710-001568   AB3006           

PCG 1            REV 02   710-001568   AB2992           

Routing Engine 0                       20000005dfae3a01  RE-2.0

MCS 0            REV 04   710-001226   AB3208           

MCS 1            REV 04   710-001226   AB3212           

SFM 0 SPP        REV 06   710-001228   AB3103           

SFM 0 SPR        REV 01   710-002189   AB2936            Internet Processor II

SFM 1 SPP        REV 07   710-001228   AG2634           

SFM 1 SPR        REV 03   710-002189   AE3503            Internet Processor II

SFM 2 SPP        REV 06   710-001228   AB2976           

SFM 2 SPR        REV 01   710-002189   AB2938            Internet Processor II

SFM 3 SPP        REV 06   710-001228   AB5826           

SFM 3 SPR        REV 01   710-002189   AB2917            Internet Processor II

FPC 0            REV 03   710-003947   HE0614            E-FPC Type 1

  CPU            REV 01   710-004600   AT3217           

  PIC 0          REV 03   750-005636   BE1826            4x CHDS3 QPP

# This is the channelized DS-3 QPP PIC.

  PIC 1          REV 07   750-003846   HG5572            1x 800M Crypto

  PIC 2          REV 01   750-004507   BA5341            10x CE1-NxDS0

  PIC 3          REV 06   750-003009   AM6929            4x CT3

#This is the original channelized CT3 PIC.

FPC 1            REV 03   710-003309   AD9434            E-FPC Type 2

  CPU            REV 05   710-001217   AH2707           

  PIC 2          REV 05   750-001900   AD5738            1x OC-48 SONET, SMSR

  PIC 3          REV 04   750-003737   BC1106            4x G/E, 1000 BASE-SX

Table 2 shows you how many channels and which interface types you can configure on channelized QPP interfaces:

Table 2: Number and Types of Channels Configurable on Channelized QPP Interfaces

Interface	1-port Channelized OC-12 QPP	4-port Channelized DS-3 QPP	10-port Channelized E1 PIC
OC-12c	1	n/a	n/a
OC-3c	4	n/a	n/a
T3	12	4 (1 per port)	n/a
T1 / Fractional T1	336	112 (28 per port)	n/a
E1 / Fractional E1	n/a	n/a	10 (1 per port)
NxDS-0	336	128 (32 per port)	310 (31 per port)

When you configure channelized QPP interfaces, keep in mind these rules of thumb:

• You normally configure media-related statements and options at the physical interface level (also known as the controller level). This level is indicated by the [edit interfaces cxx-fpc/pic/port] hierarchy level.
• You should always configure HDLC-related statements (for example, bytes, fcs, idle-cycle-flag, mtu, receive-bucket, start-end-flag, and transmit-bucket) and logical interfaces (for example, [edit interfaces interface-name unit unit-number]) on end channels such as DS-0 and T1. Never configure these statements at the controller level.
• Pay attention to the channel numbering rules:

• OC-3 SONET channels configured on channelized OC-12 QPP interfaces are numbered from 1 to 4.
• T3 channels configured on channelized OC-12 QPP interfaces are numbered from 1 to 12.
• T1 channels configured on either a channelized OC-12 QPP interface or a channelized DS-3 QPP interface are numbered from 1 to 28.
• NxDS-0 timeslots configured on either a channelized OC-12 QPP interface or a channelized DS-3 QPP interface are numbered from 1 to 24.
• NxDS-0 timeslots configured on a channelized E1 QPP interface are numbered from 1 to 31. (Timeslot 0 is reserved.)

If you use Frame Relay encapsulation on a channelized interface, see Table 3 for the number of data-link connection identifiers (DLCIs) that you can configure at each channel level.

Table 3: Frame Relay DLCI Limitations for Channelized Interfaces

Original Channelized PICs	Number of DLCIs per level	Range
T3 and T1 level channels	64 for regular mode 3 for sparse mode	0—64 for regular mode 1—1022 for sparse mode (0 is reserved for the Local Management Interface or LMI)
DS-0 level channels	3 for sparse mode	1—1022 for sparse mode (0 is reserved for LMI)
Channelized PICs with QPP	Number of DLCIs per level	Range
OC-12 and OC-3 level channels (Channelized OC-12 PIC with QPP)	64	1—1022 (0 is reserved for LMI)
T3 level channel (Channelized DS-3 or Channelized OC-12 PICs with QPP)	64	1—1022 (0 is reserved for LMI)
E1 level channels (Channelized E1 PIC with QPP)	16	1—1022 (0 is reserved for LMI)
T1 level channels (Channelized DS-3 or Channelized OC-12 PICs with QPP)	16	1—1022 (0 is reserved for LMI)
DS-0 level channels (Channelized DS-3, Channelized E1, or Channelized OC-12 PICs with QPP)	16	1—1022 (0 is reserved for LMI)

When you configure clocking, bit error rate testing (BERT), C-bit parity, and loopback statements on T3, T1, or DS-0 channels on channelized QPP interfaces, you must follow these guidelines:

• If you include the statements at both the [edit interfaces ct3-x/y/z:channel t3-options] and [edit interfaces t3-x/y/z:channel t3-options] hierarchy levels, the CT3-level statements are operational and the T3-level statements are ignored.
• If you include the statements at both the [edit interfaces ct3-x/y/z:channel t3-options] and [edit interfaces t1-x/y/z:channel t1-options] hierarchy levels, the CT3-level statements are operational for the T3 connections and the T1-level statements are operational for the T1 connections.
• Because DS-0 channels do not have a valid clocking option, you must configure clocking for all NxDS-0s at the [edit interfaces ct1-x/y/z:channel t1-options] hierarchy level.
• You can configure BERT at the [edit interfaces ct3-x/y/z:channel t3-options] hierarchy level or on any partitioned subchannel of the CT3 interface. There are twelve BERT patterns available for DS-0 channels and twenty-eight BERT patterns for T1, CT1, T3, and CT3 channels within channelized QPP interfaces.
• You can configure loopbacks at the [edit interfaces ct3-x/y/z:channel t3-options] hierarchy level and higher. Local loopbacks recirculate framing information within the local router. Remote loopbacks resend entire frames back to the remote sender. A new loopback called a payload loopback is similar to a remote loopback, but it resends only the data portion of a frame back to the remote sender.
• You can configure C-bit parity at the [edit interfaces ct3-x/y/z:channel t3-options] hierarchy level or on any partitioned subchannel of the CT3 interface.