The routers consist of the following major hardware components:
A fundamental architectural feature is the use of shared memory as the interconnect between slots. Specifically, when a packet arrives on an input interface, it is placed into a buffer where it stays until it is sent out of the output interface. This architecture has several consequences. First, given that the complexity of the system is partly due to the number of buffering stages, the architecture is relatively clean and simple. Second, the centralized buffer can support buffering for each interface that is equal to the bandwidth times the delay and therefore can meet TCP's buffering needs in order to maximize throughput. Finally, the shared memory architecture supports multicast traffic at nearly the theoretical maximum efficiency.