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Juniper was the first North American IP routing vendor to achieve the prestigious TL 9000 certification by the Quality of Excellence for Suppliers of Telecommunications (QuEST) Forum in the router category, for design, development, provision and service and support.
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M40e Packet Forwarding Engine Clock Generators (PCGs) Description
The M40e Multiservice Edge Router has two Packet Forwarding Engine Clock Generators (PCGs) installed in the slots at the rear of the chassis that are labeled PCG 0 and PCG 1, as shown in M40e Chassis Description. The PCGs generate a 125-MHz clock signal used to gate packet processing. During startup, the active Routing Engine determines which PCG is master and which is backup, and the MCS relays the decision to the PCGs and to the modules and ASICs in the Packet Forwarding Engine that use the clock signal. The modules and ASICs then use only the signal from the master source.
PCGs are hot-pluggable, as described in M40e Field-Replaceable Units (FRUs). Removal or failure of the backup PCG does not affect router function. When the master PCG fails or is removed from the chassis, however, the Packet Forwarding Engine resets so that the components start using the signal from the other PCG (which becomes the master). The Packet Forwarding Engine cannot accept incoming packets until each PFE component, including the SFM and FPCs, resets to recognize the new master PCG. This can result in traffic halting for several minutes.
For PCG replacement instructions, see Replacing a PCG in an M40e Router.
Figure 1: M40e PCG Component
Figure 2 shows the location of the PCGs on the M40e and M160 router chassis.
Figure 2: M40e and M160 Router PCG Location
