Packet Forwarding Engine Architecture for T Series Routers

Packet Forwarding Engine Components

• Layer 2/Layer 3 Packet Processing ASIC, which performs Layer 2 and Layer 3 encapsulation and decapsulation, and manages the division and reassembly of packets within the router.
• Queuing and Memory Interface ASICs, which manage the buffering of data cells in memory and the queueing of notifications.
• T Series Internet Processor, which provides the route lookup function.
• Switch Interface ASICs, which extract the route lookup key and manage the flow of data cells across the switch fabric.
• Media-specific ASICs on the PICs which perform control functions tailored to the PIC media types.

Data Flow Through the T Series Router

To ensure the efficient movement of data, the router is designed so that ASICs on the hardware components handle the forwarding of data. Data flows through the router in the following sequence (see Figure 1):

Figure 1: Data Flow Through the Router

1. Packets arrive at an incoming PIC interface.
2. The PIC passes the packets to the FPC, where the Layer 2/Layer 3 Packet Processing ASIC performs Layer 2 and Layer 3 parsing and divides the packets into 64-byte cells.
3. The Switch Interface ASIC extracts the route lookup key, places it in a notification, and passes the notification to the T Series Internet Processor. The Switch Interface ASIC also passes the data cells to the Queuing and Memory Interface ASICs for buffering.
4. The Queuing and Memory Interface ASICs pass the data cells to memory for buffering.
5. The T Series Internet Processor performs the route lookup and forwards the notification to the Queuing and Memory Interface ASIC.
6. The Queuing and Memory Interface ASIC sends the notification to the Switch Interface ASIC facing the switch fabric, unless the destination is on the same Packet Forwarding Engine. In this case, the notification is sent back to the Switch Interface ASIC facing the outgoing ports, and the packets are sent to the outgoing port without passing through the switch fabric (see Step 13).
7. The Switch Interface ASIC sends bandwidth requests through the switch fabric to the destination port. The Switch Interface ASIC also issues read requests to the Queuing and Memory Interface ASIC to begin reading data cells out of memory.
8. The destination Switch Interface ASIC sends bandwidth grants through the switch fabric to the originating Switch Interface ASIC.
9. Upon receipt of each bandwidth grant, the originating Switch Interface ASIC sends a cell through the switch fabric to the destination Packet Forwarding Engine.
10. The destination Switch Interface ASIC receives cells from the switch fabric. It extracts the route lookup key from each cell, places it in a notification, and forwards the notification to the T Series Internet Processor.
11. The T Series Internet Processor performs the route lookup, and forwards the notification to the Queuing and Memory Interface ASIC.
12. The Queuing and Memory Interface ASIC forwards the notification, including next-hop information, to the Switch Interface ASIC.
13. The Switch Interface ASIC sends read requests to the Queuing and Memory Interface ASIC to read the data cells out of memory, and passes the cells to the Layer 2/Layer 3 Packet Processing ASIC.
14. The Layer 2/Layer 3 Packet Processing ASIC reassembles the data cells into packets, adds Layer 2 encapsulation, and sends the packets to the outgoing PIC interface.
15. The outgoing PIC sends the packets out into the network.