In JUNOSe releases earlier than Release 10.2.x, ATM Martini circuit functionality was supported on ERX14xx models, ERX7xx models, and the ERX310 router that enabled the ATM cells that pertained to a particular ATM virtual circuit (VC) to be transported over a single pseudowire. This behavior was achieved by emulating connectivity between two ATM ports for a single virtual circuit. However, if you wanted to emulate the connectivity between two ATM ports instead of between ATM VCs using a single VC over a single pseudowire, all the necessary VCs had to be configured separately. Also, in such cases, the corresponding pseudowires for each of the VCs had to be configured individually. This method was not efficient because of the amount of manual configuration and MPLS signaling protocol (LDP) state that had to be maintained.
Now, you can emulate physical connectivity between two ATM ports that are not directly connected. This emulation is made possible by transporting ATM cells belonging to a subset of matching ATM VCs on both the ATM ports over a single pseudowire. Multiple VCs over a single psuedowire is useful in scenarios when ATM switches are connected using a high-speed packet switched network, instead of expensive physical cables.
Support for configuration of multiple ATM VCs over a single pseudowire is based on RFC 4816, Pseudowire Emulation Edge-to-Edge (PWE3) Asynchronous Transfer Mode (ATM) Transparent Cell Transport Service. Although this RFC requires all the ATM cells, corresponding to all possible ATM virtual circuits, received on an ATM port to be transported on the associated single pseudowire, the current implementation does not enable all possible ATM virtual circuits on an ATM port to be transported. This condition occurs because of hardware limitations on the ATM line modules supported on ERX14xx models, ERX7xx models, and the ERX310 router. As a result, it is necessary to explicitly open virtual circuits on the segmentation and reassembly (SAR) scheduler to enable ATM cells corresponding to those virtual circuits to be received and transported over a pseudowire. Because of the scaling limitations on the number of virtual circuits that can be opened on the SAR scheduler, all possible ATM virtual circuits for a single ATM port cannot be opened on the SAR device. Therefore, to enable multiple VCs over a single pseudowire to be configured on the ERX routers, you must specify the subset of ATM virtual circuits on a port that must be carried on the single pseudowire.
To configure the subset of ATM virtual circuits, you must configure a VPI/VCI range using the new mpls-relay atm vpi-range vpiStart vpiEnd vci-range vciStart vciEnd command in global configuration mode. You can configure this VPI/VCI range only for ATM ports for which you have associated a pseudowire using the MPLS Martini circuit configuration. Before the support for multiple ATM VCs over a single pseudowire was available, MPLS Martini circuit configuration was allowed only on ATM subinterfaces and not on ATM ports. To enable a subset of ATM virtual circuits to be transported over a single pseudowire, you must add the MPLS Martini circuit configuration on an ATM port (associating the ATM port with the single pseudowire) and then specify the subset of ATM virtual circuits whose cells need to be transported on the single pseudowire using the VPI/VCI range configuration.
You can specify a maximum of four non-overlapping VPI/VCI ranges for each ATM port. The cumulative number of ATM virtual circuits in the specified VPI/VCI ranges must not exceed the scaling limitation of the SAR scheduler. The SAR scheduler limitation is not for each port, but for the entire line module. The VPI/VCI range configurations specified on the ATM ports on both ends of the pseudowire must match. Even if the VPI/VCI range configurations do not match on both ends of the pseudowire, Label Discovery Protocol (LDP) brings up the pseudowire. However, on the remote provider edge (PE) router, ATM cells received from the pseudowire that are not within the configured ranges are discarded.
For more information on the guidelines to be followed when you configure VCI/VPI ranges for transportation of a subset of ATM VCs on a single pseudowire, see Guidelines for Configuring VPI/VCI Ranges of ATM Virtual Circuits.
You can also specify concatenation of multiple ATM cells to be sent in a single MPLS-labeled packet for efficient usage of the backbone bandwidth. If you do not specify cell concatenation, each individual ATM cell is MPLS-labeled and transmitted on the pseudowire. You can use the mpls-relay atm cell-packing mcpt-timers command to configure the following parameters that control how the router performs cell concatenation:
Based on this configuration, the router attempts to concatenate the specified maximum number of ATM cells into an MPLS packet within the time interval allowed by the ATM Martini cell packing timer you selected. When the router detects that the allotted time interval has expired, the router forwards the MPLS packet even if it contains fewer than the specified maximum number of aggregated cells per packet. The cell concatenation functionality is controlled by the timer values and the maximum number of cells to be concatenated. The LDP signaling protocol option to negotiate cell concatenation (maximum number of concatenated ATM cells) is not used.
For more information on the guidelines to be followed when you configure cell concatenation and cell packing timer identifiers for transporation of ATM VCs on a single pseudowire, see Guidelines for Configuring Cell Concatenation and Cell Packing Timer for an ATM Port.
When you add the MPLS Martini circuit configuration on an ATM port, you cannot add the interface label space RSVP configuration on the same ATM port. Therefore, you can configure an ATM port with either the interface label space RSVP configuration or the MPLS Martini circuit at the same time. You cannot configure both the interface label space RSVP configuration or the MPLS Martini circuit on the same ATM port at the same time.
The ATMx port is not changed to the Loss of Signal (LOS) state, which denotes the number of times for which the incoming optical signal is all zeros for at least 100 microseconds, when a failure is detected on the pseudowire. Possible causes might include a cable disconnection, excessive attenuation of the signal, or faulty equipment. The changeover to the LOS state for the ATM port is not performed because only a subset of the ATM virtual circuits are configured to be transported on the pseudowire. The ATM virtual circuits on the same ATM port that are not associated with the single pseudowire and are not present in the specified subset continue to function in the desired manner, without being affected by the failure detected on the pseudowire. If the ATM port was moved to an LOS state, all ATM virtual circuits on the same port that are configured for functionality other than the multiple VCs over single pseudowire functionality are also disrupted.
The F5 Operations Administration and Maintenance (OAM) cells and Integrated Local Management Interface (ILMI) cells are carried on the pseudowire because F5 OAM cells arrive with the same VPI/VCI values as the data cells. In such cases, you can configure the ILMI VPI/VCI as part of the range to enable the ILMI cells be carried on the pseudowire. However, F4 OAM cells are not carried over the pseudowire because the router does not enable opening of the VP-level OAM circuits to be transported transparently on the pseudowire. Because only a subset of the ATM virtual circuits on an ATM port are carried on the pseudowire, LDP uses the ATM n-to-one VCC cell transport (0x0009) pseudowire (PW) type instead of the ATM transparent cell transport (0x0003) PW type in the signaling messages.
Observe the following guidelines when you specify a single VPI/VCI range of ATM VCs whose cells need to be transported on the single pseudowire:
Observe the following guidelines when you configure the maximum number of ATM cells that the router can concatenate in a single packet and the identifier of the ATM Martini cell packing timer that you want to use to detect timeout of the cell collection threshold:
Because the support for multiple ATM VCs over a single pseudowire requires one pseudowire per ATM port and the number of ATM ports in a fully populated ERX chassis is in the order of a few tens of ports, the number of pseudowires required is also of the same range. As a result, no performance impact is caused by LDP signaling and state management. The amount of memory needed and initial CPU activity on the line module for a specified range are proportional to the number of VCs in the range.
You can scale the number of virtual circuits configured on an ATM line module up to 16,000. The VPI/VCI range specification on the ATM ports for this feature is controlled by this limit. Depending on other VPI/VCI configuration on the ATM line module, the range specification must not be greater than this scaled limit subtracted from the other VPI/VCI configuration.
A VPI/VCI range with the maximum number of VCs does not cause the line module to become unstable. Support for unified ISSU and high availability with a VPI/VCI range configured with the maximum number of VCs is provided.