When a packet enters an M-series or T-series Juniper Networks router, the Physical Interface Card (PIC) receiving the packet retrieves it from the network and verifies that the link-layer information is valid. The packet is then passed to the Flexible PIC Concentrator (FPC), where the data link and network layer information is verified. In addition, the FPC is responsible for segmenting the packet into 64-byte units called J-cells. These cells are then written into packet storage memory while a notification cell is sent to the route lookup engine. The destination address listed in the notification cell is located in the forwarding table, and the next hop of the packet is written into the result cell. This result cell is queued on the appropriate outbound FPC until the outgoing interface is ready to transmit the packet. The FPC then reads the J-cells out of memory, re-forms the original packet, and sends the packet to the outgoing PIC, where it is transmitted back into the network.
Packet flow differs by platform type. This section discusses the following topics:
On J-series Services Routers, some of the hardware components associated with larger platforms are virtualized. These virtualized components include Packet Forwarding Engines, Routing Engines, and their associated ASICs. For this reason, packet flow on J-series routers cannot be described in terms of discrete hardware components.
On M-series routers, CoS actions are performed in several locations in a Juniper Networks router: the incoming I/O Manager ASIC, the Internet Processor II ASIC, and the outgoing I/O Manager ASIC. These locations are shown in Figure 2.
Figure 2: M-series Packet Forwarding Engine Components and Data Flow
The following sections describe the packet flow in more detail:
When a data packet is passed from the receiving interface to its connected FPC, it is received by the I/O Manager ASIC on that specific FPC. During the processing of the packet by this ASIC, the information in the packet’s header is examined by a behavior aggregate (BA) classifier. This classification action associates the packet with a particular forwarding class. In addition, the value of the packet’s loss priority bit is set by this classifier. Both the forwarding class and loss priority information are placed into the notification cell, which is then transmitted to the Internet Processor II ASIC.
The Internet Processor II ASIC receives notification cells representing inbound data packets and performs route lookups in the forwarding table. This lookup determines the outgoing interface on the router and the next-hop IP address for the data packet. While the packet is being processed by the Internet Processor II ASIC, it might also be evaluated by a firewall filter, which is configured on either the incoming or outgoing interface. This filter can perform the functions of a multifield (MF) classifier by matching on multiple elements within the packet and overwriting the forwarding class, loss priority settings, or both within the notification cell. Once the route lookup and filter evaluations are complete, the notification cell, now called the result cell, is passed to the I/O Manager ASIC on the FPC associated with the outgoing interface.
When the result cell is received by the I/O Manager ASIC, it is placed into a queue to await transmission on the physical media. The specific queue used by the ASIC is determined by the forwarding class associated with the data packet. The configuration of the queue itself helps determine the service the packet receives while in this queued state. This functionality guarantees that certain packets are serviced and transmitted before other packets. In addition, the queue settings and the packet’s loss priority setting determine which packets might be dropped from the network during periods of congestion.
In addition to queuing the packet, the outgoing I/O Manager ASIC is responsible for ensuring that CoS bits in the packet’s header are correctly set before it is transmitted. This rewrite function helps the next downstream router perform its CoS function in the network.
The Enhanced Compact Forwarding Engine Board (CFEB-E) for the M7i and M10i routers provides additional hardware performance, scaling, and functions, as well as enhanced CoS software capabilities.
The enhanced CoS functions available with the CFEB-E on M7i and M10i routers include:
The CoS architecture for MX-series Ethernet services routers such as the MX960 router is similar in concept, but different in particulars, from other routing platforms. The general architecture for the MX-series routing platform is shown in Figure 3.
Figure 3: MX-series Packet Forwarding and Data Flow
 |
Note: In spite of the similarity in designation, the MX-series architecture is different from the M-series routers. However, all Layer 3 JUNOS software CoS functions are supported on the MX-series Ethernet Services routers. In addition, Layer 3 CoS capabilities, with the exception of traffic shaping, are supported on virtual LANs (VLANs) that span multiple ports. |
The MX-series routing platform can classify incoming packets at the ingress Dense Port Concentrator (DPC). Fixed classification places all packets in the same forwarding class, or the usual MF or BA classifications can be used to treat packets differently. BA classification with firewall filters can be used for classification based on IP precedence, DSCP, IEEE, or other bits in the frame or packet header.
However, the MX-series routing platforms can also employ multiple BA classifiers on the same logical interface. The logical interfaces do not have to employ the same type of BA classifier. For example, a single logical interface can use classifiers based on IP precedence as well as IEEE 802.1p. If the CoS bits of interest are on the inner VLAN tag of a dual-tagged VLAN interface, the classifier can examine either the inner or outer bits. (By default, the classification is done based on the outer VLAN tag.)
Internal fabric scheduling is based on only two queues: high and low priority. Strict-high priority queuing is also supported in the high-priority category.
Egress port scheduling supports up to eight queues per port using a form of round-robin queue servicing. The supported priority levels are strict-high, high, medium-high, medium-low, and low. The MX-series architecture supports both early discard and tail drop on the queues.
All CoS features are supported at line rate.
The fundamental flow of a packet subjected to CoS is different in the MX-series with integrated chips than it is in the M-series and T-series routers, which have a different packet-handling architecture.
The way that a packet makes its way through an M-series or T-series router with Intelligent Queuing 2 (IQ2) PICs is shown in Figure 4. Note that the per-VLAN scheduling and shaping are done on the PIC whereas all other CoS functions at the port level are performed on the Packet Forwarding Engine.
Figure 4: Packet Handling on the M-series and T-series Routers
The way that a packet makes its way through an MX-series router with Enhanced Queuing DPCs is shown in Figure 5. Note that the scheduling and shaping are done with an integrated architecture on the DPC along with all other CoS functions. In particular, scheduling and shaping are done on the Ethernet services engine network processing unit (ESE NPU). Hierarchical scheduling is supported on the output side only.
Figure 5: Packet Handling on the MX-series Routers
MX-series routers, especially the MX960 Ethernet Services router, have several features that differ from the usual CoS features in the JUNOS software as described in Packet Flow Through the CoS Process.
The MX960 router allows fixed classification of traffic. All packets on a logical interface can be put into the same forwarding class:
As on other platforms, the MX-series routers allow BA classification, the classifying of packets into different forwarding classes (up to eight) based on a value in the packet header. However, MX-series routers allow a mixture of BA classifiers (IEEE 802.1p and others) for logical interfaces on the same port, as shown in the following example:
- [edit class-of-service interfaces ge-0/0/0 unit 0]
- classifiers {
- inet-precedence IPPRCE-BA-1;
- ieee-802.1 DOT1P-BA-1;
- }
In this case, the IEEE classifier is applied to Layer 2 traffic and the Internet precedence classifier is applied to Layer 3 (IP) traffic. The IEEE classifier can also perform BA classification based on the bits of either the inner or outer VLAN tag on a dual-tagged logical interface, as shown in the following example:
- [edit class-of-service interfaces ge-0/0/0]
- unit 0 {
-
- classifiers {
-
- ieee-802.1 DOT1-BA-1 {
- vlan-tag inner;
- }
- }
- }
- unit 1 {
-
- classifiers {
-
- ieee-802.1 DOT1-BA-1 {
- vlan-tag outer;
- }
- }
- }
The default action is based on the outer VLAN tag’s IEEE precedence bits.
As on other platforms, the BA classification can be overridden with a multifield classifier in the action part of a firewall filter. Rewrites are handled as on other platforms, but MX-series routers support classifications and rewrites for aggregated Ethernet (ae-) logical interfaces.
On MX-series routers, the 64 classifier limit is a theoretical upper limit. In practice, you cannot configure 64 classifiers. Three values are used internally by the default IP precedence, IPv6, and EXP classifiers. Two other classifiers are used for forwarding class and queue operations. This leaves 59 classifiers for configuration purposes. If you configure Differentiated Services code point (DSCP) rewrites for MPLS, the maximum number of classifiers you can configure is less than 59.
On MX-series routers, IEEE 802.1 classifier bit rewrites are determined by forwarding class and packet priority, not by queue number and packet priority as on other platforms.
On T-series routing platforms, CoS actions are performed in several locations: the incoming and outgoing Switch Interface ASICs, the T-series Internet Processor ASIC, and the Queuing and Memory Interface ASICs. These locations are shown in Figure 6.
Figure 6: T-series Packet Forwarding Engine Components and Data Flow
The following sections describe the packet flow in more detail:
When a data packet is passed from the receiving interface to its connected FPC, it is received by the incoming Switch Interface ASIC on that specific FPC. During the processing of the packet by this ASIC, the information in the packet’s header is examined by a BA classifier. This classification action associates the packet with a particular forwarding class. In addition, the value of the packet’s loss priority bit is set by this classifier. Both the forwarding class and loss priority information are placed into the notification cell, which is then transmitted to the T-series Internet Processor ASIC.
The T-series Internet Processor ASIC receives notification cells representing inbound data packets and performs route lookups in the forwarding table. This lookup determines the outgoing interface on the router and the next-hop IP address for the data packet. While the packet is being processed by the T-series Internet Processor ASIC, it might also be evaluated by a firewall filter, which is configured on either the incoming or outgoing interface. This filter can perform the functions of an MF classifier by matching on multiple elements within the packet and overwriting the forwarding class settings, loss priority settings, or both within the notification cell. Once the route lookup and filter evaluations are complete, the notification cell, now called the result cell, is passed to the Queuing and Memory Interface ASICs.
The Queuing and Memory Interface ASICs pass the data cells to memory for buffering. The data cells are placed into a queue to await transmission on the physical media. The specific queue used by the ASICs is determined by the forwarding class associated with the data packet. The configuration of the queue itself helps determine the service the packet receives while in this queued state. This functionality guarantees that certain packets are serviced and transmitted before other packets. In addition, the queue settings and the packet’s loss priority setting determine which packets might be dropped from the network during periods of congestion.
In addition to queuing the packet, the outgoing I/O Manager ASIC is responsible for ensuring that CoS bits in the packet’s header are correctly set before it is transmitted. This rewrite function helps the next downstream router perform its CoS function in the network.
The Queuing and Memory Interface ASIC sends the notification to the Switch Interface ASIC facing the switch fabric, unless the destination is on the same Packet Forwarding Engine. In this case, the notification is sent back to the Switch Interface ASIC facing the outgoing ports, and the packets are sent to the outgoing port without passing through the switch fabric. The default behavior is for fabric priority queuing on egress interfaces to match the scheduling priority you assign. High-priority egress traffic is automatically assigned to high-priority fabric queues.
The Queuing and Memory Interface ASIC forwards the notification, including next-hop information, to the outgoing Switch Interface ASIC.
The destination Switch Interface ASIC sends bandwidth grants through the switch fabric to the originating Switch Interface ASIC. The Queuing and Memory Interface ASIC forwards the notification, including next-hop information, to the Switch Interface ASIC. The Switch Interface ASIC sends read requests to the Queuing and Memory Interface ASIC to read the data cells out of memory, and passes the cells to the Layer 2 or Layer 3 Packet Processing ASIC. The Layer 2 or Layer 3 Packet Processing ASIC reassembles the data cells into packets, adds Layer 2 encapsulation, and sends the packets to the outgoing PIC interface. The outgoing PIC sends the packets out into the network.
