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Home > Support > Technical Documentation > Junos OS > q-pic-large-buffer
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Related Documentation

  • M Series
  • Configuring the Junos OS to Enable Larger Delay Buffers for T1, E1, and DS0 Interfaces Configured on Channelized IQ PICs
  • MX Series
  • Configuring the Junos OS to Enable Larger Delay Buffers for T1, E1, and DS0 Interfaces Configured on Channelized IQ PICs
  • T Series
  • Configuring the Junos OS to Enable Larger Delay Buffers for T1, E1, and DS0 Interfaces Configured on Channelized IQ PICs
  • Additional Information
  • Junos Class of Service Configuration Guide PDF Document
 

q-pic-large-buffer

Syntax

q-pic-large-buffer (large-scale | small-scale);

Hierarchy Level

[edit chassis fpc slot-number pic pic-number][edit chassis lcc number fpc slot-number pic pic-number (Routing Matrix)

Release Information

Statement introduced in Junos OS Release 7.4.

Description

Configure delay buffers.

Note: When you commit the configuration after including the q-pic-large-buffer statement for a PIC, the Junos OS temporarily takes the PIC offline and brings it back online before the new configuration is activated and becomes the current operational configuration.

Default

small-scale

Options

large-scale—(Optional) Set the average packet size used to calculate the number of notification queue entries in the IQ PIC to 256 bytes. Useful for slower interfaces (T1, E1, and NxDS0 interfaces configured on Channelized IQ PICs and Gigabit Ethernet VLANs configured on Gigabit Ethernet IQ PICs).

small-scale—(Optional) Set the average packet size used to calculate the number of notification queue entries in the IQ PIC to 40 bytes.

Note: You cannot configure the large-scale and the small-scale options on MX Series routers. Include only the q-pic-large-buffer statement to enable the large delay buffer size on Enhanced Queuing DPCs on MX Series routers.

Required Privilege Level

interface—To view this statement in the configuration.

interface-control—To add this statement to the configuration.

 

Related Documentation

  • M Series
  • Configuring the Junos OS to Enable Larger Delay Buffers for T1, E1, and DS0 Interfaces Configured on Channelized IQ PICs
  • MX Series
  • Configuring the Junos OS to Enable Larger Delay Buffers for T1, E1, and DS0 Interfaces Configured on Channelized IQ PICs
  • T Series
  • Configuring the Junos OS to Enable Larger Delay Buffers for T1, E1, and DS0 Interfaces Configured on Channelized IQ PICs
  • Additional Information
  • Junos Class of Service Configuration Guide PDF Document
 

Published: 2012-03-05

 
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