Locate Phase Lock Loop Alarms

Problem

The phase lock loop (PLL) alarm occurs when the PLL cannot lock on to a timing device, and indicates a possible hardware or network timing problem.

Solution

To display SONET alarms and errors, use the following Junos OS CLI operational mode command:

user@host> show interfaces so-fpc/pic/port extensive

Sample Output

user@host> show interfaces so-1/1/1 extensive

[...Output truncated...]
Active alarms  : PLL
  Active defects : PLL
  SONET PHY:            Seconds        Count  State
    PLL Lock                 26            0  PLL Lock Error
    PHY Light                 0            0  OK
  SONET section:
    BIP-B1                    0            0
    SEF                       0            0  OK
    LOS                       0            0  OK
    LOF                       0            0  OK
    ES-S                      0
    SES-S                     0
    SEFS-S                    0
  SONET line:
    BIP-B2                    0            0
    REI-L                     0            0
    RDI-L                     3            3  OK
    AIS-L                     0            0  OK
    BERR-SF                   0            0  OK
    BERR-SD                   0            0  OK
    ES-L                      0
    SES-L                     0
    UAS-L                     0
    ES-LFE                    0
    SES-LFE                   0
    UAS-LFE                   0
  SONET path:
    BIP-B3                    0            0
    REI-P                     0            0
    LOP-P                     0            0  OK
    AIS-P                     0            0  OK
    RDI-P                     0            0  OK
    UNEQ-P                    0            0  OK
    PLM-P                     0            0  OK
    ES-P                      0
    SES-P                     0
    UAS-P                     0
    ES-PFE                    0
    SES-PFE                   0
    UAS-PFE                   0
[...Output truncated...]

Meaning

The sample output shows a PLL alarm lasting for 26 seconds. You must investigate the timing source to diagnose the problem. The timing source is derived from an incoming SONET circuit (when clock external is configured), or from the onboard Stratum 3 clock (when clock internal is configured). Internal clocking is the default for Juniper Networks routers.

The cause of the problem differs depending on the type of system board on the router. (See Table 32.) For example:

On the M20 and M40 Internet router OC48-SM-IR PIC and the M160 Internet router OC192 board, the problem might be caused by the following:

An out-of-tolerance clock coming from the far end, if clocking external is configured.

An out-of-tolerance clock coming from the far end or a problem with the board being unable to lock on to its internal clock to derive the transmit clock, if clocking internal is configured.
On OC3 and OC12 PICs, the PIC not establishing a lock to the onboard clock to derive the outgoing clock.

To further diagnose the problem, try the following:

Configure clocking to external. If the alarm disappears, the board might not have locked to the internal clock used to derive the outgoing clock.
Configure clocking to internal and make sure that a loopback fiber is plugged in. If the PLL alarm persists, it is most likely a hardware problem. However, you may not be able to determine if the direction is on the inbound or outbound side of the board.

Table 32 shows the location of the onboard clock on the various system boards of Juniper Networks routers.

Table 32: Location of the Onboard Clock

Router	System Board
M5, M10, M20, and M40 routers	System Control Board (SCB), System and Switch Board (SSB), Switching and Forwarding Module (SFM), and Single Board Router (SBR)
OC48-SM-IR PIC used on the M20 and M40 routers	Flexible PIC Concentrator (FPC)
M40e and M160 routers	Miscellaneous Control Subsystem (MCS)
T-series routing platforms	SONET Clock Generator (SCG)

Locate Phase Lock Loop Alarms

Problem

Solution

Related Documentation